From: "André Draszik" <andre.draszik@linaro.org>
To: Tudor Ambarus <tudor.ambarus@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Peter Griffin <peter.griffin@linaro.org>,
Srinivas Kandagatla <srini@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
semen.protsenko@linaro.org, willmcvicker@google.com,
kernel-team@android.com, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 4/5] soc: samsung: exynos-chipid: add google,gs101-otp support
Date: Tue, 23 Dec 2025 10:18:56 +0000 [thread overview]
Message-ID: <aa55c3865d151697120a2855e711d59468bdcd0a.camel@linaro.org> (raw)
In-Reply-To: <20251222-gs101-chipid-v4-4-aa8e20ce7bb3@linaro.org>
On Mon, 2025-12-22 at 16:30 +0000, Tudor Ambarus wrote:
> GS101 is different (but also e850 and autov9 I assume) from the SoCs
> that are currently handled by the exynos-chipid driver because the
> chip ID info is part of the OTP registers. GS101 OTP has a clock, an
> interrupt line, a register space (that contains product and chip ID,
> TMU data, ASV, etc) and a 32Kbit memory space that can be
> read/program/locked with specific commands. On GS101 the "ChipID block"
> is just an abstraction, it's not a physical device. When the power-on
> sequence progresses, the OTP chipid values are loaded to the OTP
> registers.
>
> Add the GS101 chip ID support. The support is intentionally added in the
> exynos-chipid driver, and not in a dedicated Exynos OTP driver, because
> we estimate that there will not be any OTP consumers in the kernel other
> than the chip ID/SoC interface. The downstream GS101 drivers confirm
> this supposition.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
> drivers/soc/samsung/exynos-chipid.c | 70 ++++++++++++++++++++++++++++++++-----
> 1 file changed, 61 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
> index 5c8660374269c87ec38ebca242918bd7b1d362e5..6ef9751e2509c94bd9625072d0b81ddb93048d4a 100644
> --- a/drivers/soc/samsung/exynos-chipid.c
> +++ b/drivers/soc/samsung/exynos-chipid.c
> @@ -15,7 +15,8 @@
> #include <linux/array_size.h>
> #include <linux/device.h>
> #include <linux/device/devres.h>
> -#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/ioport.h>
> #include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of.h>
> @@ -28,9 +29,11 @@
> #include "exynos-asv.h"
>
> struct exynos_chipid_variant {
> - unsigned int rev_reg; /* revision register offset */
> + unsigned int main_rev_reg; /* main revision register offset */
> + unsigned int sub_rev_reg; /* sub revision register offset */
> unsigned int main_rev_shift; /* main revision offset in rev_reg */
> unsigned int sub_rev_shift; /* sub revision offset in rev_reg */
> + bool efuse;
> };
>
> struct exynos_chipid_info {
> @@ -69,6 +72,8 @@ static const struct exynos_soc_id {
> { "EXYNOS990", 0xE9830000 },
> { "EXYNOSAUTOV9", 0xAAA80000 },
> { "EXYNOSAUTOV920", 0x0A920000 },
> + /* Compatible with: google,gs101-otp */
> + { "GS101", 0x9845000 },
> };
>
> static const char *exynos_product_id_to_name(unsigned int product_id)
> @@ -93,19 +98,53 @@ static int exynos_chipid_get_chipid_info(struct device *dev,
> return dev_err_probe(dev, ret, "failed to read Product ID\n");
> soc_info->product_id = val & EXYNOS_MASK;
>
> - if (data->rev_reg != EXYNOS_CHIPID_REG_PRO_ID) {
> - ret = regmap_read(regmap, data->rev_reg, &val);
> + if (data->sub_rev_reg == EXYNOS_CHIPID_REG_PRO_ID) {
> + /* exynos4210 case */
> + main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
> + sub_rev = (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK;
> + } else {
> + unsigned int val2;
> +
> + ret = regmap_read(regmap, data->sub_rev_reg, &val2);
> if (ret < 0)
> return dev_err_probe(dev, ret,
> "failed to read revision\n");
> +
> + if (data->main_rev_reg == EXYNOS_CHIPID_REG_PRO_ID)
> + /* gs101 case */
> + main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
> + else
> + /* exynos850 case */
> + main_rev = (val2 >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
Looking closer, why is this not val? Now you're shifting the sub_rev
register value by the main rev shift, assigning the sub_rev register
value to the main rev variable.
And then, all assignments to main_rev become identical and don't need to
be duplicated.
> +
> + sub_rev = (val2 >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK;
> }
> - main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK;
> - sub_rev = (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK;
> +
> soc_info->revision = (main_rev << EXYNOS_REV_PART_SHIFT) | sub_rev;
>
> return 0;
> }
Cheers,
Andre'
next prev parent reply other threads:[~2025-12-23 10:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-22 16:30 [PATCH v4 0/5] soc: samsung: exynos-chipid: add gs101 support Tudor Ambarus
2025-12-22 16:30 ` [PATCH v4 1/5] dt-bindings: nvmem: add google,gs101-otp Tudor Ambarus
2025-12-22 16:30 ` [PATCH v4 2/5] soc: samsung: exynos-chipid: rename method Tudor Ambarus
2025-12-23 9:55 ` André Draszik
2025-12-23 10:14 ` Tudor Ambarus
2025-12-22 16:30 ` [PATCH v4 3/5] soc: samsung: exynos-chipid: downgrade dev_info to dev_dbg for soc info Tudor Ambarus
2025-12-22 16:30 ` [PATCH v4 4/5] soc: samsung: exynos-chipid: add google,gs101-otp support Tudor Ambarus
2025-12-23 9:56 ` André Draszik
2025-12-23 10:18 ` André Draszik [this message]
2025-12-23 11:23 ` André Draszik
2025-12-22 16:30 ` [PATCH v4 5/5] arm64: dts: exynos: gs101: add OTP node Tudor Ambarus
2025-12-23 10:01 ` André Draszik
2025-12-28 11:32 ` (subset) [PATCH v4 0/5] soc: samsung: exynos-chipid: add gs101 support Krzysztof Kozlowski
2025-12-28 11:33 ` Krzysztof Kozlowski
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