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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4
Date: Sun, 4 May 2025 19:11:25 +0200	[thread overview]
Message-ID: <aa8bdf4f-feb9-4355-b629-a5d7c6a43d25@kernel.org> (raw)
In-Reply-To: <CAPVz0n0Ty3QAg_9rSvV7c7EBGDigHtTAOAfkRFBcTR9fziEvQQ@mail.gmail.com>

On 04/05/2025 18:25, Svyatoslav Ryhel wrote:
> нд, 4 трав. 2025 р. о 19:23 Krzysztof Kozlowski <krzk@kernel.org> пише:
>>
>> On 03/05/2025 10:54, Svyatoslav Ryhel wrote:
>>>>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>>>>> +/*
>>>>> + * This header provides Tegra114-specific constants for binding
>>>>> + * nvidia,tegra114-car.
>>>>> + */
>>>>> +
>>>>> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
>>>>> +
>>>>> +#define TEGRA114_RESET(x)            (5 * 32 + (x))
>>>>
>>>>
>>>> Does not look like a binding, but some sort of register. Binding IDs
>>>> start from 0 (or 1) and are incremented by 1.
>>>>
>>>
>>> Hello there!
>>> This file add same logic for Tegra114 as Tegra124 currently
>>> implements, check here
>>> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/include/dt-bindings/reset/tegra124-car.h?h=v6.14.5
>>>
>>> I did not re-use Tegra124 value, though it is same, to avoid confusion
>>> in main Tegra114 device tree.
>>
>> What confusion? Why would anyone be interested in comparing numbers thus
>> getting confused by different number? These are abstract IDs.
>>
> 
> By using TEGRA124_RESET in Tegra114 device tree

Why would you use define from other SoC... and how is it related to my
comment in the first place?


Best regards,
Krzysztof

  reply	other threads:[~2025-05-04 17:11 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-21  9:55 [PATCH v1 0/3] " Svyatoslav Ryhel
2025-03-21  9:55 ` [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support Svyatoslav Ryhel
2025-06-10 11:09   ` Thierry Reding
2025-08-11  8:08     ` Svyatoslav Ryhel
2025-08-22  2:58   ` Mikko Perttunen
2025-08-22  5:21     ` Svyatoslav Ryhel
2025-08-25  3:56       ` Mikko Perttunen
2025-03-21  9:55 ` [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4 Svyatoslav Ryhel
2025-03-21 20:50   ` Krzysztof Kozlowski
2025-05-03  8:54     ` Svyatoslav Ryhel
2025-05-04 16:23       ` Krzysztof Kozlowski
2025-05-04 16:25         ` Svyatoslav Ryhel
2025-05-04 17:11           ` Krzysztof Kozlowski [this message]
2025-05-04 17:30             ` Svyatoslav Ryhel
2025-05-04 17:33               ` Krzysztof Kozlowski
2025-06-10 11:07     ` Thierry Reding
2025-06-18  9:13       ` Krzysztof Kozlowski
2025-07-09 15:10         ` Thierry Reding
2025-03-25 18:56   ` Stephen Boyd
2025-03-25 19:00     ` Svyatoslav Ryhel
2025-08-22  2:53   ` Mikko Perttunen
2025-03-21  9:55 ` [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on " Svyatoslav Ryhel
2025-08-22  3:05   ` Mikko Perttunen
2025-08-22  5:19     ` Svyatoslav Ryhel
2025-08-25  4:20       ` Mikko Perttunen
2025-08-25  4:26         ` Svyatoslav
2025-08-26  1:42           ` Mikko Perttunen

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