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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Viresh Kumar <viresh.kumar@linaro.org>,
	Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4
Date: Fri, 21 Mar 2025 21:50:09 +0100	[thread overview]
Message-ID: <aef4574b-8167-4af3-a29c-8c962b396496@kernel.org> (raw)
In-Reply-To: <20250321095556.91425-3-clamor95@gmail.com>

On 21/03/2025 10:55, Svyatoslav Ryhel wrote:
> Extend the Tegra124 driver to include DFLL configuration settings required
> for Tegra114 compatibility.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

<form letter>
Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument, so you will
not CC people just because they made one commit years ago). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.
</form letter>



> +++ b/include/dt-bindings/reset/tegra114-car.h

Filename based on compatible.

> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * This header provides Tegra114-specific constants for binding
> + * nvidia,tegra114-car.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +#define _DT_BINDINGS_RESET_TEGRA114_CAR_H
> +
> +#define TEGRA114_RESET(x)		(5 * 32 + (x))


Does not look like a binding, but some sort of register. Binding IDs
start from 0 (or 1) and are incremented by 1.

Best regards,
Krzysztof

  reply	other threads:[~2025-03-21 20:50 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-21  9:55 [PATCH v1 0/3] " Svyatoslav Ryhel
2025-03-21  9:55 ` [PATCH v1 1/3] drivers: cpufreq: add Tegra 4 support Svyatoslav Ryhel
2025-06-10 11:09   ` Thierry Reding
2025-08-11  8:08     ` Svyatoslav Ryhel
2025-08-22  2:58   ` Mikko Perttunen
2025-08-22  5:21     ` Svyatoslav Ryhel
2025-08-25  3:56       ` Mikko Perttunen
2025-03-21  9:55 ` [PATCH v1 2/3] drivers: clk: tegra: add DFLL support for Tegra 4 Svyatoslav Ryhel
2025-03-21 20:50   ` Krzysztof Kozlowski [this message]
2025-05-03  8:54     ` Svyatoslav Ryhel
2025-05-04 16:23       ` Krzysztof Kozlowski
2025-05-04 16:25         ` Svyatoslav Ryhel
2025-05-04 17:11           ` Krzysztof Kozlowski
2025-05-04 17:30             ` Svyatoslav Ryhel
2025-05-04 17:33               ` Krzysztof Kozlowski
2025-06-10 11:07     ` Thierry Reding
2025-06-18  9:13       ` Krzysztof Kozlowski
2025-07-09 15:10         ` Thierry Reding
2025-03-25 18:56   ` Stephen Boyd
2025-03-25 19:00     ` Svyatoslav Ryhel
2025-08-22  2:53   ` Mikko Perttunen
2025-03-21  9:55 ` [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on " Svyatoslav Ryhel
2025-08-22  3:05   ` Mikko Perttunen
2025-08-22  5:19     ` Svyatoslav Ryhel
2025-08-25  4:20       ` Mikko Perttunen
2025-08-25  4:26         ` Svyatoslav
2025-08-26  1:42           ` Mikko Perttunen

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