* [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A
@ 2026-10-14 17:50 Pufan Jin
2026-10-14 17:50 ` [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix Pufan Jin
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Pufan Jin @ 2026-10-14 17:50 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Michal Simek, Rob Herring
Cc: andrew, Conor Dooley, devicetree, linux-arm-kernel, linux-kernel
The ALINX EdgeBoard FZ3A is an embedded computing board from ALINX based on
the Xilinx Zynq UltraScale+ XCZU3EG SoC. The hardware was designed and
manufactured by ALINX for Baidu's AI EdgeBoard program.
This series adds the ALINX vendor prefix, documents the board compatible,
and adds a device tree for the board's PS peripherals:
- UART1 debug console
- eMMC (HS200) and microSD card
- GEM3 Ethernet with Micrel KSZ9031 PHY on the MDIO bus
- I2C0 and I2C1
- QSPI NOR flash
- PCIe
- USB 3.0 host
- DisplayPort output
Public board documentation and product links:
- https://ai.baidu.com/tech/hardware/deepkit
- https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
- https://www.alinx.com/
- https://vd100-20232-v101.readthedocs.io/zh-cn/en/VD100_S1_RSTdocument_EN/00_aboutALINX_EN.html
Tested on ALINX EdgeBoard FZ3A hardware with Linux 7.3.0-rc5: the board boots
from SD card into userspace over the serial console, gem3 negotiates
1000Mbps/Full duplex with phy-mode = "rgmii-id", and the eMMC runs in
HS200 mode.
The base DTB passes CHECK_DTBS=y without warnings, the bindings pass
dt_binding_check, and the DTS passes dt-check-style.
Apologies for the threading issues in v2 caused by an SMTP relay breakdown;
v3 is sent as a clean, unified thread and addresses all reviewer comments.
Changes in v3:
- Update author and submission email to cyan2254650260@gmail.com
- Patch 1:
- Fix legal transliteration to "Xinyi Electronic Technology (Shanghai)
Co., Ltd. (ALINX)" (Conor Dooley)
- Add website link in commit message (Conor Dooley)
- Collect Conor's Acked-by
- Patch 2:
- Collect Conor's Acked-by
- Patch 3:
- Add public board documentation and product links in commit message
and DTS header comment (Michal Simek)
- Conform to DTS coding style:
- Sort compatible before model in root node
- Sort children in natural-sort order
- Reorder properties in canonical order (phys before phy-names, etc.)
- Add required blank lines before status properties
- Alphabetize pinctrl children and pin configurations
Changes in v2:
- Use the correct vendor prefix 'alinx' instead of 'ebdee', and rename
the board and DTS file accordingly (Krzysztof Kozlowski)
- Describe the board as a single board computer with the SoC, DDR4 and
eMMC on one PCB (Andrew Lunn)
- Add the MDIO bus and describe the KSZ9031 PHY with phy-handle (Andrew Lunn)
- Enable eMMC HS200 on sdhci0: drop no-1-8-v, add pinctrl and mmc-hs200-1_8v
- Drop power-source and bias-high-impedance from pinctrl_gem3_default,
which only produce spurious warnings on pre-2023.1 PM firmware
Pufan Jin (3):
dt-bindings: vendor-prefixes: Add ALINX vendor prefix
dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
arm64: zynqmp: Add ALINX EdgeBoard FZ3A
.../bindings/soc/xilinx/xilinx.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/xilinx/Makefile | 1 +
.../xilinx/zynqmp-alinx-edgeboard-fz3a.dts | 360 ++++++++++++++++++
4 files changed, 364 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
Range-diff against v2:
1: c33ea63b7 ! 1: ceeae5872 dt-bindings: vendor-prefixes: Add ALINX vendor prefix
@@
## Metadata ##
-Author: Pufan Jin <2254650260@qq.com>
+Author: Pufan Jin <cyan2254650260@gmail.com>
## Commit message ##
dt-bindings: vendor-prefixes: Add ALINX vendor prefix
- Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
+ Add vendor prefix for ALINX (Xinyi Electronic Technology (Shanghai)
Co., Ltd.).
- Signed-off-by: Pufan Jin <2254650260@qq.com>
+ Link: https://www.alinx.com/
+ Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
+ Acked-by: Conor Dooley <conor.dooley@microchip.com>
## Documentation/devicetree/bindings/vendor-prefixes.yaml ##
@@ Documentation/devicetree/bindings/vendor-prefixes.yaml: patternProperties:
@@ Documentation/devicetree/bindings/vendor-prefixes.yaml: patternProperties:
"^alientek,.*":
description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
+ "^alinx,.*":
-+ description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
++ description: Xinyi Electronic Technology (Shanghai) Co., Ltd. (ALINX)
"^allegro,.*":
description: Allegro DVT
"^allegromicro,.*":
2: 888548b4e ! 2: da2a7b3e7 dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
@@
## Metadata ##
-Author: Pufan Jin <2254650260@qq.com>
+Author: Pufan Jin <cyan2254650260@gmail.com>
## Commit message ##
dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
Document the ALINX EdgeBoard FZ3A compatible.
- Signed-off-by: Pufan Jin <2254650260@qq.com>
+ Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
+ Acked-by: Conor Dooley <conor.dooley@microchip.com>
## Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml ##
@@ Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml: properties:
3: cd96303fb ! 3: 273fcd977 arm64: zynqmp: Add ALINX EdgeBoard FZ3A
@@
## Metadata ##
-Author: Pufan Jin <2254650260@qq.com>
+Author: Pufan Jin <cyan2254650260@gmail.com>
## Commit message ##
arm64: zynqmp: Add ALINX EdgeBoard FZ3A
@@ Commit message
The base DTB passes CHECK_DTBS=y, and the Xilinx SoC binding passes
dt_binding_check.
- Signed-off-by: Pufan Jin <2254650260@qq.com>
+ Link: https://ai.baidu.com/tech/hardware/deepkit
+ Link: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
+ Link: https://www.alinx.com/
+ Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
## arch/arm64/boot/dts/xilinx/Makefile ##
@@
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ * Device tree for the ALINX EdgeBoard FZ3A
+ * based on the Xilinx Zynq UltraScale+ XCZU3EG
+ *
++ * Product info: https://ai.baidu.com/tech/hardware/deepkit
++ * Documentation: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
++ *
+ * Copyright (c) 2026 Pufan Jin
+ */
+
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
-+ model = "ALINX EdgeBoard FZ3A";
+ compatible = "alinx,edgeboard-fz3a", "xlnx,zynqmp";
++ model = "ALINX EdgeBoard FZ3A";
+
+ aliases {
+ ethernet0 = &gem3;
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ stdout-path = "serial0:115200n8";
+ };
+
-+ dpcon: connector {
-+ compatible = "dp-connector";
-+ label = "mini-DP";
-+ type = "mini";
-+
-+ port {
-+ dpcon_in: endpoint {
-+ remote-endpoint = <&dpsub_dp_out>;
-+ };
-+ };
-+ };
-+
+ dp_aclk: clock-dp-aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ clock-frequency = <100000000>;
+ };
+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x7ff00000>;
++ dpcon: connector {
++ compatible = "dp-connector";
++ label = "mini-DP";
++ type = "mini";
++
++ port {
++ dpcon_in: endpoint {
++ remote-endpoint = <&dpsub_dp_out>;
++ };
++ };
+ };
+
+ vcc_3v3_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
-+ regulator-name = "pcie-reset";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
++ gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
++ regulator-max-microvolt = <3300000>;
++ regulator-min-microvolt = <3300000>;
++ regulator-name = "pcie-reset";
+ };
+
+ reserved_memory: reserved-memory {
++ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
-+ ranges;
+
+ linux_cma: cma {
+ compatible = "shared-dma-pool";
++ alloc-ranges = <0x0 0x0 0x0 0x7ff00000>;
+ reusable;
-+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
-+ size = <0x0 0x20000000>; /* 512MB */
-+ linux,cma-default;
++ size = <0x0 0x20000000>;
+ };
+ };
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x0 0x0 0x0 0x7ff00000>;
++ };
+};
+
+&ams_pl {
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ snps,dis_u2_susphy_quirk;
+ snps,hsphy_interface = "ulpi";
+ snps,usb3_lpm_capable;
++
+ status = "okay";
+};
+
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
+ <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+ <&zynqmp_clk GEM_TSU>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_gem3_default>;
-+ phy-mode = "rgmii-id";
+ phy-handle = <&phy0>;
++ phy-mode = "rgmii-id";
++ pinctrl-0 = <&pinctrl_gem3_default>;
++ pinctrl-names = "default";
++
+ status = "okay";
+
+ mdio {
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
-+ reg = <1>;
+ compatible = "ethernet-phy-id0022.1620";
++ reg = <1>;
+ };
+ };
+};
+
+&gpio {
+ clocks = <&lpd_lsbus>;
++
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
++ pinctrl-names = "default";
++
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
-+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
++ pinctrl-names = "default";
++
+ status = "okay";
+};
+
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+
+&pcie {
+ phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
++
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+
++ pinctrl_gem3_default: gem3-default {
++ conf {
++ groups = "ethernet3_0_grp";
++ slew-rate = <SLEW_RATE_SLOW>;
++ };
++
++ conf-mdio {
++ bias-disable;
++ groups = "mdio3_0_grp";
++ slew-rate = <SLEW_RATE_SLOW>;
++ };
++
++ conf-rx {
++ low-power-disable;
++ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
++ "MIO75";
++ };
++
++ conf-tx {
++ bias-disable;
++ low-power-enable;
++ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
++ "MIO69";
++ };
++
++ mux {
++ function = "ethernet3";
++ groups = "ethernet3_0_grp";
++ };
++
++ mux-mdio {
++ function = "mdio3";
++ groups = "mdio3_0_grp";
++ };
++ };
++
+ pinctrl_i2c0_default: i2c0-default {
+ conf {
+ bias-pull-up;
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ };
+ };
+
-+ pinctrl_usb0_default: usb0-default {
-+ mux {
-+ function = "usb0";
-+ groups = "usb0_0_grp";
-+ };
-+ };
-+
+ pinctrl_sdhci0_default: sdhci0-default {
-+ mux {
-+ groups = "sdio0_0_grp";
-+ function = "sdio0";
-+ };
-+
+ conf {
++ bias-disable;
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
-+ bias-disable;
+ };
-+ };
+
-+ /*
-+ * Omit 'power-source' and 'bias-high-impedance' to avoid spurious
-+ * warnings on the board's pre-2023.1 PM firmware. Bank voltage
-+ * and pin directions are already configured by hardware.
-+ */
-+ pinctrl_gem3_default: gem3-default {
+ mux {
-+ function = "ethernet3";
-+ groups = "ethernet3_0_grp";
-+ };
-+
-+ conf {
-+ groups = "ethernet3_0_grp";
-+ slew-rate = <SLEW_RATE_SLOW>;
-+ };
-+
-+ conf-rx {
-+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
-+ "MIO75";
-+ low-power-disable;
-+ };
-+
-+ conf-tx {
-+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
-+ "MIO69";
-+ bias-disable;
-+ low-power-enable;
-+ };
-+
-+ mux-mdio {
-+ function = "mdio3";
-+ groups = "mdio3_0_grp";
++ function = "sdio0";
++ groups = "sdio0_0_grp";
+ };
++ };
+
-+ conf-mdio {
-+ groups = "mdio3_0_grp";
-+ slew-rate = <SLEW_RATE_SLOW>;
-+ bias-disable;
++ pinctrl_usb0_default: usb0-default {
++ mux {
++ function = "usb0";
++ groups = "usb0_0_grp";
+ };
+ };
+};
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+&psgtr {
+ clocks = <>r_refclk0>, <>r_refclk1>, <>r_refclk2>;
+ clock-names = "ref0", "ref1", "ref2";
++
+ status = "okay";
+};
+
+&qspi {
+ clocks = <&zynqmp_clk QSPI_REF>, <&lpd_lsbus>;
+ num-cs = <1>;
++
+ status = "okay";
+
+ flash: flash@0 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
++ #address-cells = <1>;
++ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+};
+
+&sdhci0 {
++ assigned-clock-rates = <187498125>;
++ bus-width = <8>;
++ cap-mmc-hw-reset;
+ clocks = <&zynqmp_clk SDIO0_REF>, <&lpd_lsbus>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_sdhci0_default>;
-+ non-removable;
+ disable-wp;
++ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
-+ mmc-hs200-1_8v;
-+ cap-mmc-hw-reset;
-+ bus-width = <8>;
++ non-removable;
++ pinctrl-0 = <&pinctrl_sdhci0_default>;
++ pinctrl-names = "default";
+ xlnx,mio-bank = <0>;
-+ assigned-clock-rates = <187498125>;
++
+ status = "okay";
+};
+
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ clocks = <&zynqmp_clk SDIO1_REF>, <&lpd_lsbus>;
+ disable-wp;
+ no-1-8-v;
++
+ status = "okay";
+};
+
+&uart0 {
+ clocks = <&zynqmp_clk UART0_REF>, <&lpd_lsbus>;
++
+ status = "okay";
+};
+
+&uart1 {
+ clocks = <&zynqmp_clk UART1_REF>, <&lpd_lsbus>;
++
+ status = "okay";
+};
+
+&usb0 {
-+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
-+ pinctrl-names = "default";
++ phy-names = "usb3-phy";
+ pinctrl-0 = <&pinctrl_usb0_default>;
++ pinctrl-names = "default";
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
@@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
-+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 3 PHY_TYPE_DP 0 2>,
+ <&psgtr 2 PHY_TYPE_DP 1 2>;
++ phy-names = "dp-phy0", "dp-phy1";
++
+ status = "okay";
+};
--
2.56.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix
2026-10-14 17:50 [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A Pufan Jin
@ 2026-10-14 17:50 ` Pufan Jin
2026-10-14 17:50 ` [PATCH v3 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A Pufan Jin
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Pufan Jin @ 2026-10-14 17:50 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Michal Simek, Rob Herring
Cc: andrew, Conor Dooley, devicetree, linux-arm-kernel, linux-kernel
Add vendor prefix for ALINX (Xinyi Electronic Technology (Shanghai)
Co., Ltd.).
Link: https://www.alinx.com/
Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Update author and submission email to cyan2254650260@gmail.com
- Fix transliteration of legal company name to "Xinyi Electronic Technology
(Shanghai) Co., Ltd. (ALINX)" (Conor Dooley)
- Add website Link in commit message (Conor Dooley)
- Collect Conor's Acked-by
Changes in v2:
- Use 'alinx' instead of 'ebdee' (Krzysztof Kozlowski)
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969..26d5ef6d7 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -90,6 +90,8 @@ patternProperties:
description: AlgolTek, Inc.
"^alientek,.*":
description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
+ "^alinx,.*":
+ description: Xinyi Electronic Technology (Shanghai) Co., Ltd. (ALINX)
"^allegro,.*":
description: Allegro DVT
"^allegromicro,.*":
--
2.56.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
2026-10-14 17:50 [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A Pufan Jin
2026-10-14 17:50 ` [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix Pufan Jin
@ 2026-10-14 17:50 ` Pufan Jin
2026-10-14 17:50 ` [PATCH v3 3/3] arm64: zynqmp: " Pufan Jin
2026-11-04 11:06 ` [PATCH v3 0/3] arm64: zynqmp: Add support for " Michal Simek
3 siblings, 0 replies; 5+ messages in thread
From: Pufan Jin @ 2026-10-14 17:50 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Michal Simek, Rob Herring
Cc: andrew, Conor Dooley, devicetree, linux-arm-kernel, linux-kernel
Document the ALINX EdgeBoard FZ3A compatible.
Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Update author and submission email to cyan2254650260@gmail.com
- Collect Conor's Acked-by
Changes in v2:
- Use 'alinx,edgeboard-fz3a' instead of 'ebdee,edgeboard-fz3a'
(Krzysztof Kozlowski)
Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df..ad7c71f9b 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -46,6 +46,7 @@ properties:
- items:
- enum:
+ - alinx,edgeboard-fz3a
- xlnx,zynqmp-zc1751
- const: xlnx,zynqmp
--
2.56.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 3/3] arm64: zynqmp: Add ALINX EdgeBoard FZ3A
2026-10-14 17:50 [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A Pufan Jin
2026-10-14 17:50 ` [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix Pufan Jin
2026-10-14 17:50 ` [PATCH v3 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A Pufan Jin
@ 2026-10-14 17:50 ` Pufan Jin
2026-11-04 11:06 ` [PATCH v3 0/3] arm64: zynqmp: Add support for " Michal Simek
3 siblings, 0 replies; 5+ messages in thread
From: Pufan Jin @ 2026-10-14 17:50 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski, Michal Simek, Rob Herring
Cc: andrew, Conor Dooley, devicetree, linux-arm-kernel, linux-kernel
Add device tree for the ALINX EdgeBoard FZ3A, a single board computer
based on the Xilinx Zynq UltraScale+ XCZU3EG SoC.
Supported peripherals:
- UART1 debug console
- eMMC (HS200) and microSD card
- GEM3 Ethernet with Micrel KSZ9031 PHY on the MDIO bus
- I2C0 and I2C1
- QSPI NOR flash
- PCIe
- USB 3.0 host
- DisplayPort output
Tested on hardware with Linux 7.3.0-rc5: the board boots from SD card
into userspace over the serial console, gem3 negotiates 1000Mbps/Full
duplex with phy-mode = "rgmii-id", and the eMMC runs in HS200 mode.
The base DTB passes CHECK_DTBS=y, and the Xilinx SoC binding passes
dt_binding_check.
Link: https://ai.baidu.com/tech/hardware/deepkit
Link: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
Link: https://www.alinx.com/
Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
---
Changes in v3:
- Update author and submission email to cyan2254650260@gmail.com
- Add public board documentation and product links in commit message
and DTS header comment (Michal Simek)
- Conform to DTS coding style:
- Sort compatible before model in root node
- Sort children in natural-sort order
- Reorder properties in canonical order (phys before phy-names, etc.)
- Add required blank lines before status properties
- Alphabetize pinctrl children and pin configurations
Changes in v2:
- Rename to 'zynqmp-alinx-edgeboard-fz3a.dts' using 'alinx' prefix
(Krzysztof Kozlowski)
- Describe the board as a single board computer with the SoC, DDR4 and
eMMC on one PCB, not a carrier board with a MYIR SoM (Andrew Lunn)
- Add the MDIO bus and describe the KSZ9031 PHY with phy-handle (Andrew Lunn)
- Enable eMMC HS200 on sdhci0: drop no-1-8-v, add pinctrl and mmc-hs200-1_8v
- Drop power-source and bias-high-impedance from pinctrl_gem3_default,
which only produce spurious warnings on pre-2023.1 PM firmware
arch/arm64/boot/dts/xilinx/Makefile | 1 +
.../xilinx/zynqmp-alinx-edgeboard-fz3a.dts | 360 ++++++++++++++++++
2 files changed, 361 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 70fac0b27..3e07b36ef 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-alinx-edgeboard-fz3a.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts b/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
new file mode 100644
index 000000000..6cad90091
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for the ALINX EdgeBoard FZ3A
+ * based on the Xilinx Zynq UltraScale+ XCZU3EG
+ *
+ * Product info: https://ai.baidu.com/tech/hardware/deepkit
+ * Documentation: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
+ *
+ * Copyright (c) 2026 Pufan Jin
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+ compatible = "alinx,edgeboard-fz3a", "xlnx,zynqmp";
+ model = "ALINX EdgeBoard FZ3A";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ dp_aclk: clock-dp-aclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ gtr_refclk0: clock-gtr-ref0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ gtr_refclk1: clock-gtr-ref1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ gtr_refclk2: clock-gtr-ref2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ /*
+ * Vendor TF-A 1.8.1 does not register LPD_LSBUS (ID 31) into CCF.
+ * Provide a fixed-clock fallback for bus peripherals to probe.
+ */
+ lpd_lsbus: clock-lpd-lsbus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ dpcon: connector {
+ compatible = "dp-connector";
+ label = "mini-DP";
+ type = "mini";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
+
+ vcc_3v3_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "pcie-reset";
+ };
+
+ reserved_memory: reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux_cma: cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x0 0x0 0x7ff00000>;
+ reusable;
+ size = <0x0 0x20000000>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x7ff00000>;
+ };
+};
+
+&ams_pl {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&dwc3_0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,hsphy_interface = "ulpi";
+ snps,usb3_lpm_capable;
+
+ status = "okay";
+};
+
+&gem3 {
+ clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
+ <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+ <&zynqmp_clk GEM_TSU>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0022.1620";
+ reg = <1>;
+ };
+ };
+};
+
+&gpio {
+ clocks = <&lpd_lsbus>;
+
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
+&pcie {
+ phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
+
+ status = "okay";
+};
+
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ conf-mdio {
+ bias-disable;
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ conf-rx {
+ low-power-disable;
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ };
+
+ conf-tx {
+ bias-disable;
+ low-power-enable;
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ conf {
+ bias-pull-up;
+ groups = "i2c0_8_grp";
+ };
+
+ mux {
+ function = "i2c0";
+ groups = "i2c0_8_grp";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ bias-pull-up;
+ groups = "i2c1_8_grp";
+ };
+
+ mux {
+ function = "i2c1";
+ groups = "i2c1_8_grp";
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ conf {
+ bias-disable;
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ function = "sdio0";
+ groups = "sdio0_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ function = "usb0";
+ groups = "usb0_0_grp";
+ };
+ };
+};
+
+&psgtr {
+ clocks = <>r_refclk0>, <>r_refclk1>, <>r_refclk2>;
+ clock-names = "ref0", "ref1", "ref2";
+
+ status = "okay";
+};
+
+&qspi {
+ clocks = <&zynqmp_clk QSPI_REF>, <&lpd_lsbus>;
+ num-cs = <1>;
+
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&sdhci0 {
+ assigned-clock-rates = <187498125>;
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ clocks = <&zynqmp_clk SDIO0_REF>, <&lpd_lsbus>;
+ disable-wp;
+ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
+ pinctrl-names = "default";
+ xlnx,mio-bank = <0>;
+
+ status = "okay";
+};
+
+&sdhci1 {
+ clocks = <&zynqmp_clk SDIO1_REF>, <&lpd_lsbus>;
+ disable-wp;
+ no-1-8-v;
+
+ status = "okay";
+};
+
+&uart0 {
+ clocks = <&zynqmp_clk UART0_REF>, <&lpd_lsbus>;
+
+ status = "okay";
+};
+
+&uart1 {
+ clocks = <&zynqmp_clk UART1_REF>, <&lpd_lsbus>;
+
+ status = "okay";
+};
+
+&usb0 {
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+ phy-names = "usb3-phy";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ clocks = <&dp_aclk>,
+ <&zynqmp_clk DP_AUDIO_REF>,
+ <&zynqmp_clk DP_VIDEO_REF>;
+ clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
+ phys = <&psgtr 3 PHY_TYPE_DP 0 2>,
+ <&psgtr 2 PHY_TYPE_DP 1 2>;
+ phy-names = "dp-phy0", "dp-phy1";
+
+ status = "okay";
+};
--
2.56.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A
2026-10-14 17:50 [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A Pufan Jin
` (2 preceding siblings ...)
2026-10-14 17:50 ` [PATCH v3 3/3] arm64: zynqmp: " Pufan Jin
@ 2026-11-04 11:06 ` Michal Simek
3 siblings, 0 replies; 5+ messages in thread
From: Michal Simek @ 2026-11-04 11:06 UTC (permalink / raw)
To: Pufan Jin, Conor Dooley, Krzysztof Kozlowski, Rob Herring
Cc: andrew, Conor Dooley, devicetree, linux-arm-kernel, linux-kernel
On 10/14/26 19:50, Pufan Jin wrote:
> The ALINX EdgeBoard FZ3A is an embedded computing board from ALINX based on
> the Xilinx Zynq UltraScale+ XCZU3EG SoC. The hardware was designed and
> manufactured by ALINX for Baidu's AI EdgeBoard program.
>
> This series adds the ALINX vendor prefix, documents the board compatible,
> and adds a device tree for the board's PS peripherals:
> - UART1 debug console
> - eMMC (HS200) and microSD card
> - GEM3 Ethernet with Micrel KSZ9031 PHY on the MDIO bus
> - I2C0 and I2C1
> - QSPI NOR flash
> - PCIe
> - USB 3.0 host
> - DisplayPort output
>
> Public board documentation and product links:
> - https://ai.baidu.com/tech/hardware/deepkit
> - https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
> - https://www.alinx.com/
> - https://vd100-20232-v101.readthedocs.io/zh-cn/en/VD100_S1_RSTdocument_EN/00_aboutALINX_EN.html
>
> Tested on ALINX EdgeBoard FZ3A hardware with Linux 7.3.0-rc5: the board boots
> from SD card into userspace over the serial console, gem3 negotiates
> 1000Mbps/Full duplex with phy-mode = "rgmii-id", and the eMMC runs in
> HS200 mode.
>
> The base DTB passes CHECK_DTBS=y without warnings, the bindings pass
> dt_binding_check, and the DTS passes dt-check-style.
>
> Apologies for the threading issues in v2 caused by an SMTP relay breakdown;
> v3 is sent as a clean, unified thread and addresses all reviewer comments.
>
> Changes in v3:
> - Update author and submission email to cyan2254650260@gmail.com
> - Patch 1:
> - Fix legal transliteration to "Xinyi Electronic Technology (Shanghai)
> Co., Ltd. (ALINX)" (Conor Dooley)
> - Add website link in commit message (Conor Dooley)
> - Collect Conor's Acked-by
> - Patch 2:
> - Collect Conor's Acked-by
> - Patch 3:
> - Add public board documentation and product links in commit message
> and DTS header comment (Michal Simek)
> - Conform to DTS coding style:
> - Sort compatible before model in root node
> - Sort children in natural-sort order
> - Reorder properties in canonical order (phys before phy-names, etc.)
> - Add required blank lines before status properties
> - Alphabetize pinctrl children and pin configurations
>
> Changes in v2:
> - Use the correct vendor prefix 'alinx' instead of 'ebdee', and rename
> the board and DTS file accordingly (Krzysztof Kozlowski)
> - Describe the board as a single board computer with the SoC, DDR4 and
> eMMC on one PCB (Andrew Lunn)
> - Add the MDIO bus and describe the KSZ9031 PHY with phy-handle (Andrew Lunn)
> - Enable eMMC HS200 on sdhci0: drop no-1-8-v, add pinctrl and mmc-hs200-1_8v
> - Drop power-source and bias-high-impedance from pinctrl_gem3_default,
> which only produce spurious warnings on pre-2023.1 PM firmware
>
>
> Pufan Jin (3):
> dt-bindings: vendor-prefixes: Add ALINX vendor prefix
> dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
> arm64: zynqmp: Add ALINX EdgeBoard FZ3A
>
> .../bindings/soc/xilinx/xilinx.yaml | 1 +
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> arch/arm64/boot/dts/xilinx/Makefile | 1 +
> .../xilinx/zynqmp-alinx-edgeboard-fz3a.dts | 360 ++++++++++++++++++
> 4 files changed, 364 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts
>
> Range-diff against v2:
> 1: c33ea63b7 ! 1: ceeae5872 dt-bindings: vendor-prefixes: Add ALINX vendor prefix
> @@
> ## Metadata ##
> -Author: Pufan Jin <2254650260@qq.com>
> +Author: Pufan Jin <cyan2254650260@gmail.com>
>
> ## Commit message ##
> dt-bindings: vendor-prefixes: Add ALINX vendor prefix
>
> - Add vendor prefix for ALINX (Shanghai Xin'yi Electronics Technology
> + Add vendor prefix for ALINX (Xinyi Electronic Technology (Shanghai)
> Co., Ltd.).
>
> - Signed-off-by: Pufan Jin <2254650260@qq.com>
> + Link: https://www.alinx.com/
> + Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
> + Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> ## Documentation/devicetree/bindings/vendor-prefixes.yaml ##
> @@ Documentation/devicetree/bindings/vendor-prefixes.yaml: patternProperties:
> @@ Documentation/devicetree/bindings/vendor-prefixes.yaml: patternProperties:
> "^alientek,.*":
> description: Guangzhou Xingyi Intelligent Technology Co., Ltd.
> + "^alinx,.*":
> -+ description: Shanghai Xin'yi Electronics Technology Co., Ltd. (ALINX)
> ++ description: Xinyi Electronic Technology (Shanghai) Co., Ltd. (ALINX)
> "^allegro,.*":
> description: Allegro DVT
> "^allegromicro,.*":
> 2: 888548b4e ! 2: da2a7b3e7 dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
> @@
> ## Metadata ##
> -Author: Pufan Jin <2254650260@qq.com>
> +Author: Pufan Jin <cyan2254650260@gmail.com>
>
> ## Commit message ##
> dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A
>
> Document the ALINX EdgeBoard FZ3A compatible.
>
> - Signed-off-by: Pufan Jin <2254650260@qq.com>
> + Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
> + Acked-by: Conor Dooley <conor.dooley@microchip.com>
>
> ## Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml ##
> @@ Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml: properties:
> 3: cd96303fb ! 3: 273fcd977 arm64: zynqmp: Add ALINX EdgeBoard FZ3A
> @@
> ## Metadata ##
> -Author: Pufan Jin <2254650260@qq.com>
> +Author: Pufan Jin <cyan2254650260@gmail.com>
>
> ## Commit message ##
> arm64: zynqmp: Add ALINX EdgeBoard FZ3A
> @@ Commit message
> The base DTB passes CHECK_DTBS=y, and the Xilinx SoC binding passes
> dt_binding_check.
>
> - Signed-off-by: Pufan Jin <2254650260@qq.com>
> + Link: https://ai.baidu.com/tech/hardware/deepkit
> + Link: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
> + Link: https://www.alinx.com/
> + Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
>
> ## arch/arm64/boot/dts/xilinx/Makefile ##
> @@
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + * Device tree for the ALINX EdgeBoard FZ3A
> + * based on the Xilinx Zynq UltraScale+ XCZU3EG
> + *
> ++ * Product info: https://ai.baidu.com/tech/hardware/deepkit
> ++ * Documentation: https://ai.baidu.com/ai-doc/HWCE/8kq9b2121
> ++ *
> + * Copyright (c) 2026 Pufan Jin
> + */
> +
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> +#include "zynqmp-clk-ccf.dtsi"
> +
> +/ {
> -+ model = "ALINX EdgeBoard FZ3A";
> + compatible = "alinx,edgeboard-fz3a", "xlnx,zynqmp";
> ++ model = "ALINX EdgeBoard FZ3A";
> +
> + aliases {
> + ethernet0 = &gem3;
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + stdout-path = "serial0:115200n8";
> + };
> +
> -+ dpcon: connector {
> -+ compatible = "dp-connector";
> -+ label = "mini-DP";
> -+ type = "mini";
> -+
> -+ port {
> -+ dpcon_in: endpoint {
> -+ remote-endpoint = <&dpsub_dp_out>;
> -+ };
> -+ };
> -+ };
> -+
> + dp_aclk: clock-dp-aclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + clock-frequency = <100000000>;
> + };
> +
> -+ memory@0 {
> -+ device_type = "memory";
> -+ reg = <0x0 0x0 0x0 0x7ff00000>;
> ++ dpcon: connector {
> ++ compatible = "dp-connector";
> ++ label = "mini-DP";
> ++ type = "mini";
> ++
> ++ port {
> ++ dpcon_in: endpoint {
> ++ remote-endpoint = <&dpsub_dp_out>;
> ++ };
> ++ };
> + };
> +
> + vcc_3v3_pcie: regulator-pcie {
> + compatible = "regulator-fixed";
> -+ regulator-name = "pcie-reset";
> -+ regulator-min-microvolt = <3300000>;
> -+ regulator-max-microvolt = <3300000>;
> -+ gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> ++ gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
> + regulator-boot-on;
> ++ regulator-max-microvolt = <3300000>;
> ++ regulator-min-microvolt = <3300000>;
> ++ regulator-name = "pcie-reset";
> + };
> +
> + reserved_memory: reserved-memory {
> ++ ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> -+ ranges;
> +
> + linux_cma: cma {
> + compatible = "shared-dma-pool";
> ++ alloc-ranges = <0x0 0x0 0x0 0x7ff00000>;
> + reusable;
> -+ alloc-ranges = <0x0 0x0 0x0 0x80000000>;
> -+ size = <0x0 0x20000000>; /* 512MB */
> -+ linux,cma-default;
> ++ size = <0x0 0x20000000>;
> + };
> + };
> ++
> ++ memory@0 {
> ++ device_type = "memory";
> ++ reg = <0x0 0x0 0x0 0x7ff00000>;
> ++ };
> +};
> +
> +&ams_pl {
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + snps,dis_u2_susphy_quirk;
> + snps,hsphy_interface = "ulpi";
> + snps,usb3_lpm_capable;
> ++
> + status = "okay";
> +};
> +
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
> + <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
> + <&zynqmp_clk GEM_TSU>;
> -+ pinctrl-names = "default";
> -+ pinctrl-0 = <&pinctrl_gem3_default>;
> -+ phy-mode = "rgmii-id";
> + phy-handle = <&phy0>;
> ++ phy-mode = "rgmii-id";
> ++ pinctrl-0 = <&pinctrl_gem3_default>;
> ++ pinctrl-names = "default";
> ++
> + status = "okay";
> +
> + mdio {
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + #size-cells = <0>;
> +
> + phy0: ethernet-phy@1 {
> -+ reg = <1>;
> + compatible = "ethernet-phy-id0022.1620";
> ++ reg = <1>;
> + };
> + };
> +};
> +
> +&gpio {
> + clocks = <&lpd_lsbus>;
> ++
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <400000>;
> -+ pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c0_default>;
> ++ pinctrl-names = "default";
> ++
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> -+ pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_default>;
> ++ pinctrl-names = "default";
> ++
> + status = "okay";
> +};
> +
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> +
> +&pcie {
> + phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
> ++
> + status = "okay";
> +};
> +
> +&pinctrl0 {
> + status = "okay";
> +
> ++ pinctrl_gem3_default: gem3-default {
> ++ conf {
> ++ groups = "ethernet3_0_grp";
> ++ slew-rate = <SLEW_RATE_SLOW>;
> ++ };
> ++
> ++ conf-mdio {
> ++ bias-disable;
> ++ groups = "mdio3_0_grp";
> ++ slew-rate = <SLEW_RATE_SLOW>;
> ++ };
> ++
> ++ conf-rx {
> ++ low-power-disable;
> ++ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
> ++ "MIO75";
> ++ };
> ++
> ++ conf-tx {
> ++ bias-disable;
> ++ low-power-enable;
> ++ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
> ++ "MIO69";
> ++ };
> ++
> ++ mux {
> ++ function = "ethernet3";
> ++ groups = "ethernet3_0_grp";
> ++ };
> ++
> ++ mux-mdio {
> ++ function = "mdio3";
> ++ groups = "mdio3_0_grp";
> ++ };
> ++ };
> ++
> + pinctrl_i2c0_default: i2c0-default {
> + conf {
> + bias-pull-up;
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + };
> + };
> +
> -+ pinctrl_usb0_default: usb0-default {
> -+ mux {
> -+ function = "usb0";
> -+ groups = "usb0_0_grp";
> -+ };
> -+ };
> -+
> + pinctrl_sdhci0_default: sdhci0-default {
> -+ mux {
> -+ groups = "sdio0_0_grp";
> -+ function = "sdio0";
> -+ };
> -+
> + conf {
> ++ bias-disable;
> + groups = "sdio0_0_grp";
> + slew-rate = <SLEW_RATE_SLOW>;
> -+ bias-disable;
> + };
> -+ };
> +
> -+ /*
> -+ * Omit 'power-source' and 'bias-high-impedance' to avoid spurious
> -+ * warnings on the board's pre-2023.1 PM firmware. Bank voltage
> -+ * and pin directions are already configured by hardware.
> -+ */
> -+ pinctrl_gem3_default: gem3-default {
> + mux {
> -+ function = "ethernet3";
> -+ groups = "ethernet3_0_grp";
> -+ };
> -+
> -+ conf {
> -+ groups = "ethernet3_0_grp";
> -+ slew-rate = <SLEW_RATE_SLOW>;
> -+ };
> -+
> -+ conf-rx {
> -+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
> -+ "MIO75";
> -+ low-power-disable;
> -+ };
> -+
> -+ conf-tx {
> -+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
> -+ "MIO69";
> -+ bias-disable;
> -+ low-power-enable;
> -+ };
> -+
> -+ mux-mdio {
> -+ function = "mdio3";
> -+ groups = "mdio3_0_grp";
> ++ function = "sdio0";
> ++ groups = "sdio0_0_grp";
> + };
> ++ };
> +
> -+ conf-mdio {
> -+ groups = "mdio3_0_grp";
> -+ slew-rate = <SLEW_RATE_SLOW>;
> -+ bias-disable;
> ++ pinctrl_usb0_default: usb0-default {
> ++ mux {
> ++ function = "usb0";
> ++ groups = "usb0_0_grp";
> + };
> + };
> +};
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> +&psgtr {
> + clocks = <>r_refclk0>, <>r_refclk1>, <>r_refclk2>;
> + clock-names = "ref0", "ref1", "ref2";
> ++
> + status = "okay";
> +};
> +
> +&qspi {
> + clocks = <&zynqmp_clk QSPI_REF>, <&lpd_lsbus>;
> + num-cs = <1>;
> ++
> + status = "okay";
> +
> + flash: flash@0 {
> -+ #address-cells = <1>;
> -+ #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> ++ #address-cells = <1>;
> ++ #size-cells = <1>;
> + spi-max-frequency = <50000000>;
> + spi-rx-bus-width = <4>;
> + spi-tx-bus-width = <1>;
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> +};
> +
> +&sdhci0 {
> ++ assigned-clock-rates = <187498125>;
> ++ bus-width = <8>;
> ++ cap-mmc-hw-reset;
> + clocks = <&zynqmp_clk SDIO0_REF>, <&lpd_lsbus>;
> -+ pinctrl-names = "default";
> -+ pinctrl-0 = <&pinctrl_sdhci0_default>;
> -+ non-removable;
> + disable-wp;
> ++ mmc-hs200-1_8v;
> + no-sd;
> + no-sdio;
> -+ mmc-hs200-1_8v;
> -+ cap-mmc-hw-reset;
> -+ bus-width = <8>;
> ++ non-removable;
> ++ pinctrl-0 = <&pinctrl_sdhci0_default>;
> ++ pinctrl-names = "default";
> + xlnx,mio-bank = <0>;
> -+ assigned-clock-rates = <187498125>;
> ++
> + status = "okay";
> +};
> +
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + clocks = <&zynqmp_clk SDIO1_REF>, <&lpd_lsbus>;
> + disable-wp;
> + no-1-8-v;
> ++
> + status = "okay";
> +};
> +
> +&uart0 {
> + clocks = <&zynqmp_clk UART0_REF>, <&lpd_lsbus>;
> ++
> + status = "okay";
> +};
> +
> +&uart1 {
> + clocks = <&zynqmp_clk UART1_REF>, <&lpd_lsbus>;
> ++
> + status = "okay";
> +};
> +
> +&usb0 {
> -+ phy-names = "usb3-phy";
> + phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
> -+ pinctrl-names = "default";
> ++ phy-names = "usb3-phy";
> + pinctrl-0 = <&pinctrl_usb0_default>;
> ++ pinctrl-names = "default";
> + reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
> +
> + status = "okay";
> @@ arch/arm64/boot/dts/xilinx/zynqmp-alinx-edgeboard-fz3a.dts (new)
> + <&zynqmp_clk DP_AUDIO_REF>,
> + <&zynqmp_clk DP_VIDEO_REF>;
> + clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
> -+ phy-names = "dp-phy0", "dp-phy1";
> + phys = <&psgtr 3 PHY_TYPE_DP 0 2>,
> + <&psgtr 2 PHY_TYPE_DP 1 2>;
> ++ phy-names = "dp-phy0", "dp-phy1";
> ++
> + status = "okay";
> +};
Applied.
M
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-11-04 11:06 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2026-10-14 17:50 [PATCH v3 0/3] arm64: zynqmp: Add support for ALINX EdgeBoard FZ3A Pufan Jin
2026-10-14 17:50 ` [PATCH v3 1/3] dt-bindings: vendor-prefixes: Add ALINX vendor prefix Pufan Jin
2026-10-14 17:50 ` [PATCH v3 2/3] dt-bindings: soc: xilinx: Add ALINX EdgeBoard FZ3A Pufan Jin
2026-10-14 17:50 ` [PATCH v3 3/3] arm64: zynqmp: " Pufan Jin
2026-11-04 11:06 ` [PATCH v3 0/3] arm64: zynqmp: Add support for " Michal Simek
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