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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: quic_utiwari@quicinc.com, herbert@gondor.apana.org.au,
	thara.gopinath@gmail.com, davem@davemloft.net
Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, quic_neersoni@quicinc.com
Subject: Re: [PATCH v7] crypto: qce - Add runtime PM and interconnect bandwidth scaling support
Date: Fri, 20 Feb 2026 10:52:04 +0100	[thread overview]
Message-ID: <ab5725df-8454-4e3d-8806-a711ef0e6a42@oss.qualcomm.com> (raw)
In-Reply-To: <20260220072818.2921517-1-quic_utiwari@quicinc.com>

On 2/20/26 8:28 AM, quic_utiwari@quicinc.com wrote:
> From: Udit Tiwari <quic_utiwari@quicinc.com>
> 
> The Qualcomm Crypto Engine (QCE) driver currently lacks support for
> runtime power management (PM) and interconnect bandwidth control.
> As a result, the hardware remains fully powered and clocks stay
> enabled even when the device is idle. Additionally, static
> interconnect bandwidth votes are held indefinitely, preventing the
> system from reclaiming unused bandwidth.
> 
> Address this by enabling runtime PM and dynamic interconnect
> bandwidth scaling to allow the system to suspend the device when idle
> and scale interconnect usage based on actual demand. Improve overall
> system efficiency by reducing power usage and optimizing interconnect
> resource allocation.

[...]


> +static int __maybe_unused qce_runtime_suspend(struct device *dev)

I think you should be able to drop __maybe_unused if you drop the
SET_ prefix in pm_ops and add a pm_ptr() around &qce_crypto_pm_ops in
the assignment at the end

> +{
> +	struct qce_device *qce = dev_get_drvdata(dev);
> +
> +	icc_disable(qce->mem_path);

icc_disable() can also fail, since under the hood it's an icc_set(path, 0, 0),
please check its retval

> +
> +	return pm_clk_suspend(dev);
> +}
> +
> +static int __maybe_unused qce_runtime_resume(struct device *dev)
> +{
> +	struct qce_device *qce = dev_get_drvdata(dev);
> +	int ret = 0;

No need to initialize it here, as you overwrite this zero immediately
a line below anyway

> +
> +	ret = pm_clk_resume(dev);
> +	if (ret)
> +		return ret;
> +
> +	ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH);
> +	if (ret)
> +		goto err_icc;

Normally I think bus votes are cast before clock re-enables to make sure
the hw doesn't try to access a disabled bus path

Konrad

> +
> +	return 0;
> +
> +err_icc:
> +	pm_clk_suspend(dev);
> +	return ret;
> +}
> +
> +static const struct dev_pm_ops qce_crypto_pm_ops = {
> +	SET_RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL)
> +	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
> +};
> +
>  static const struct of_device_id qce_crypto_of_match[] = {
>  	{ .compatible = "qcom,crypto-v5.1", },
>  	{ .compatible = "qcom,crypto-v5.4", },
> @@ -261,6 +323,7 @@ static struct platform_driver qce_crypto_driver = {
>  	.driver = {
>  		.name = KBUILD_MODNAME,
>  		.of_match_table = qce_crypto_of_match,
> +		.pm = &qce_crypto_pm_ops,
>  	},
>  };
>  module_platform_driver(qce_crypto_driver);

  reply	other threads:[~2026-02-20  9:52 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-20  7:28 quic_utiwari
2026-02-20  9:52 ` Konrad Dybcio [this message]
2026-02-21  4:00   ` Bjorn Andersson
2026-02-23 13:14     ` Konrad Dybcio
2026-02-20 14:34 ` kernel test robot
2026-02-20 20:44 ` kernel test robot
2026-02-20 23:39 ` Bjorn Andersson
2026-03-04  5:30   ` Udit Tiwari

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