From: David Laight <David.Laight@ACULAB.COM>
To: 'Sebastian Andrzej Siewior' <bigeasy@linutronix.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "x86@kernel.org" <x86@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>
Subject: RE: [PATCH 1/3] x86/mm/pat: Disable preemption around __flush_tlb_all()
Date: Wed, 17 Oct 2018 09:54:38 +0000 [thread overview]
Message-ID: <acaca255a70b411488b889db9d1c31e4@AcuMS.aculab.com> (raw)
In-Reply-To: <20181016202525.29437-2-bigeasy@linutronix.de>
From: Sebastian Andrzej Siewior
> Sent: 16 October 2018 21:25
> I've seen the WARN_ON_ONCE(__read_cr3() != build_cr3()) in
> switch_mm_irqs_off() every once in a while during a snapshotted system
> upgrade.
> I also saw the warning early during which was introduced in commit
> decab0888e6e ("x86/mm: Remove preempt_disable/enable() from
> __native_flush_tlb()"). The callchain is
>
> get_page_from_freelist() -> post_alloc_hook() -> __kernel_map_pages()
>
> with CONFIG_DEBUG_PAGEALLOC enabled.
>
> Turns out, once I disable preemption around __flush_tlb_all() both
> warnings do not appear.
>
> Disable preemption during CR3 reset / __flush_tlb_all().
>
> Fixes: decab0888e6e ("x86/mm: Remove preempt_disable/enable() from __native_flush_tlb()")
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> arch/x86/mm/pageattr.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
> index 51a5a69ecac9f..fe6b21f0a6631 100644
> --- a/arch/x86/mm/pageattr.c
> +++ b/arch/x86/mm/pageattr.c
> @@ -2088,7 +2088,9 @@ void __kernel_map_pages(struct page *page, int numpages, int enable)
> * We should perform an IPI and flush all tlbs,
> * but that can deadlock->flush only current cpu:
> */
> + preempt_disable();
> __flush_tlb_all();
> + preempt_enable();
Can it make any sense to flush the tlb with preemption enabled?
Surely preemption must be disabled over something else as well?
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2018-10-17 9:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-16 20:25 [0/3] A few 32bit x86 fixes Sebastian Andrzej Siewior
2018-10-16 20:25 ` [PATCH 1/3] x86/mm/pat: Disable preemption around __flush_tlb_all() Sebastian Andrzej Siewior
2018-10-16 21:25 ` Andy Lutomirski
2018-10-16 21:38 ` Sebastian Andrzej Siewior
2018-10-16 23:28 ` Andy Lutomirski
2018-10-17 10:34 ` [PATCH 1/3 v2] " Sebastian Andrzej Siewior
2018-10-29 18:10 ` [tip:x86/urgent] " tip-bot for Sebastian Andrzej Siewior
2018-11-05 21:56 ` Dan Williams
2018-10-17 9:54 ` David Laight [this message]
2018-10-17 10:39 ` [PATCH 1/3] " 'Sebastian Andrzej Siewior'
2018-10-17 11:45 ` David Laight
2018-10-17 12:00 ` 'Sebastian Andrzej Siewior'
2018-10-17 11:11 ` Peter Zijlstra
2018-10-17 11:17 ` Thomas Gleixner
2018-10-17 15:47 ` Peter Zijlstra
2018-10-17 15:55 ` Thomas Gleixner
2018-10-17 16:00 ` 'Sebastian Andrzej Siewior'
2018-10-17 16:22 ` Peter Zijlstra
2018-10-16 20:25 ` [PATCH 2/3] x86/fpu: Remove second definition of fpu in __fpu__restore_sig() Sebastian Andrzej Siewior
2018-10-16 21:26 ` Andy Lutomirski
2018-10-17 9:09 ` [tip:x86/urgent] " tip-bot for Sebastian Andrzej Siewior
2018-10-18 6:22 ` tip-bot for Sebastian Andrzej Siewior
2018-10-16 20:25 ` [PATCH 3/3] x86/fpu: Save FPU registers on context switch if there is a FPU Sebastian Andrzej Siewior
2018-10-16 23:00 ` Andy Lutomirski
2018-10-17 9:10 ` [tip:x86/urgent] x86/fpu: Fix i486 + no387 boot crash by only saving FPU registers on context switch if there is an FPU tip-bot for Sebastian Andrzej Siewior
2018-10-18 6:22 ` tip-bot for Sebastian Andrzej Siewior
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