[PATCH v7 0/3] Fix degradation problem of alpha blending series

[PATCH v7 0/3] Fix degradation problem of alpha blending series

[Jason-JH.Lin]

Some SoCs not support pre-multiplied pixel formats and extending
configuration of OVL pre-multiplied color formats, such as MT8173.

Fix the SoC degradation problem by this sreies.

---

Change in v7:
1. Add the remove color format comment patch for OVL
2. Fix warning: 'const' type qualifier on return type has no effect

Chnage in v6:
1. Use blend_modes instead of function pointer in OVL
2. Use ethdr instead of mdp_rdma to get blend_modes
3. Add 0 checking for adding blend_mode property for mtk_plane

Change in v5:
Add fix patch for mtk_plane

Change in v4:
Add lost cases of mtk_ovl_fmt_convert_with_blend

Change in v3:
Change MACRO approach to function pointer in driver data

Change in v2:
Fix build error and typo

Change in v1:
Add fix patch for OVL unsupport color format settings by driver data

---

Jason-JH.Lin (3):
  drm/mediatek: ovl: Remove the color format comment for
    ovl_fmt_convert()
  drm/mediatek: ovl: Add blend_modes to driver data
  drm/mediatek: Add blend_modes to mtk_plane_init() for different SoCs

 drivers/gpu/drm/mediatek/mtk_crtc.c           |  1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c       |  2 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h       | 10 ++++
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |  2 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       | 48 ++++++++++++++++---
 .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c   |  7 +++
 drivers/gpu/drm/mediatek/mtk_ethdr.c          |  7 +++
 drivers/gpu/drm/mediatek/mtk_ethdr.h          |  1 +
 drivers/gpu/drm/mediatek/mtk_plane.c          | 15 +++---
 drivers/gpu/drm/mediatek/mtk_plane.h          |  4 +-
 10 files changed, 80 insertions(+), 17 deletions(-)

-- 
2.43.0

[PATCH v7 1/3] drm/mediatek: ovl: Remove the color format comment for ovl_fmt_convert()

[Jason-JH.Lin]

Since we changed MACROs to be consistent with DRM input color format
naming, the comment for ovl_fmt_conver() is no longer needed.

Fixes: 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in OVL")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 89b439dcf3a6..4a4bc27a67f0 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -389,11 +389,6 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,
 				    unsigned int blend_mode)
 {
-	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
-	 * is defined in mediatek HW data sheet.
-	 * The alphabet order in XXX is no relation to data
-	 * arrangement in memory.
-	 */
 	switch (fmt) {
 	default:
 	case DRM_FORMAT_RGB565:
-- 
2.43.0

[PATCH v7 2/3] drm/mediatek: ovl: Add blend_modes to driver data

[Jason-JH.Lin]

OVL_CON_CLRFMT_MAN is a configuration for extending color format
settings of DISP_REG_OVL_CON(n).
It will change some of the original color format settings.

Take the settings of (3 << 12) for example.
- If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA8888.
- If OVL_CON_CLRFMT_MAN = 1 means OVL_CON_CLRFMT_PARGB8888.

Since previous SoCs did not support OVL_CON_CLRFMT_MAN, this means
that the SoC does not support the premultiplied color format.
It will break the original color format setting of MT8173.

Therefore, the blend_modes is added to the driver data and then
mtk_ovl_fmt_convert() will check the blend_modes to see if
premultiplied supported in current platform.
If it is not supported, use coverage mode to set it to the supported
color formats to solve the degradation problem.

Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OVL")
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 38 +++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4a4bc27a67f0..0cf7b80f612e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -146,6 +146,7 @@ struct mtk_disp_ovl_data {
 	bool fmt_rgb565_is_0;
 	bool smi_id_en;
 	bool supports_afbc;
+	const u32 blend_modes;
 	const u32 *formats;
 	size_t num_formats;
 	bool supports_clrfmt_ext;
@@ -386,9 +387,23 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
 		      DISP_REG_OVL_RDMA_CTRL(idx));
 }
 
-static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,
-				    unsigned int blend_mode)
+static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,
+					struct mtk_plane_state *state)
 {
+	unsigned int fmt = state->pending.format;
+	unsigned int blend_mode = state->base.pixel_blend_mode;
+
+	/*
+	 * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware data sheet
+	 * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB8888.
+	 *
+	 * Check blend_modes in the driver data to see if premultiplied mode is supported.
+	 * If not, use coverage mode instead to set it to the supported color formats.
+	 */
+	if (!(ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) &&
+	    blend_mode == DRM_MODE_BLEND_PREMULTI)
+		blend_mode = DRM_MODE_BLEND_COVERAGE;
+
 	switch (fmt) {
 	default:
 	case DRM_FORMAT_RGB565:
@@ -466,7 +481,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 		return;
 	}
 
-	con = ovl_fmt_convert(ovl, fmt, blend_mode);
+	con = mtk_ovl_fmt_convert(ovl, state);
 	if (state->base.fb) {
 		con |= OVL_CON_AEN;
 		con |= state->base.alpha & OVL_CON_ALPHA;
@@ -621,6 +636,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = false,
+	.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -630,6 +647,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
 	.gmc_bits = 8,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -639,6 +658,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
 	.gmc_bits = 10,
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -648,6 +669,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
 	.gmc_bits = 10,
 	.layer_nr = 2,
 	.fmt_rgb565_is_0 = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -658,6 +681,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
 	.layer_nr = 4,
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
+		       BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -668,6 +694,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
 	.layer_nr = 2,
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
+		       BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8173_formats,
 	.num_formats = ARRAY_SIZE(mt8173_formats),
 };
@@ -679,6 +708,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
 	.fmt_rgb565_is_0 = true,
 	.smi_id_en = true,
 	.supports_afbc = true,
+	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
+		       BIT(DRM_MODE_BLEND_COVERAGE) |
+		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
 	.formats = mt8195_formats,
 	.num_formats = ARRAY_SIZE(mt8195_formats),
 	.supports_clrfmt_ext = true,
-- 
2.43.0

[PATCH v7 3/3] drm/mediatek: Add blend_modes to mtk_plane_init() for different SoCs

[Jason-JH.Lin]

Since some SoCs support premultiplied pixel formats but some do not,
the blend_modes parameter is added to mtk_plane_init(), which is
obtained from the mtk_ddp_comp_get_blend_modes function implemented
in different blending supported components.

The blending supported components can use driver data to set the
blend mode capabilities for different SoCs.

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_crtc.c             |  1 +
 drivers/gpu/drm/mediatek/mtk_ddp_comp.c         |  2 ++
 drivers/gpu/drm/mediatek/mtk_ddp_comp.h         | 10 ++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_drv.h         |  2 ++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c         |  7 +++++++
 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c |  7 +++++++
 drivers/gpu/drm/mediatek/mtk_ethdr.c            |  7 +++++++
 drivers/gpu/drm/mediatek/mtk_ethdr.h            |  1 +
 drivers/gpu/drm/mediatek/mtk_plane.c            | 15 +++++++--------
 drivers/gpu/drm/mediatek/mtk_plane.h            |  4 ++--
 10 files changed, 46 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 175b00e5a253..b65f196f2015 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -913,6 +913,7 @@ static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
 				BIT(pipe),
 				mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
 				mtk_ddp_comp_supported_rotations(comp),
+				mtk_ddp_comp_get_blend_modes(comp),
 				mtk_ddp_comp_get_formats(comp),
 				mtk_ddp_comp_get_num_formats(comp), i);
 		if (ret)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index be66d94be361..edc6417639e6 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -363,6 +363,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
 	.layer_config = mtk_ovl_layer_config,
 	.bgclr_in_on = mtk_ovl_bgclr_in_on,
 	.bgclr_in_off = mtk_ovl_bgclr_in_off,
+	.get_blend_modes = mtk_ovl_get_blend_modes,
 	.get_formats = mtk_ovl_get_formats,
 	.get_num_formats = mtk_ovl_get_num_formats,
 };
@@ -416,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
 	.disconnect = mtk_ovl_adaptor_disconnect,
 	.add = mtk_ovl_adaptor_add_comp,
 	.remove = mtk_ovl_adaptor_remove_comp,
+	.get_blend_modes = mtk_ovl_adaptor_get_blend_modes,
 	.get_formats = mtk_ovl_adaptor_get_formats,
 	.get_num_formats = mtk_ovl_adaptor_get_num_formats,
 	.mode_valid = mtk_ovl_adaptor_mode_valid,
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index ecf6dc283cd7..39720b27f4e9 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -80,6 +80,7 @@ struct mtk_ddp_comp_funcs {
 	void (*ctm_set)(struct device *dev,
 			struct drm_crtc_state *state);
 	struct device * (*dma_dev_get)(struct device *dev);
+	u32 (*get_blend_modes)(struct device *dev);
 	const u32 *(*get_formats)(struct device *dev);
 	size_t (*get_num_formats)(struct device *dev);
 	void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
@@ -266,6 +267,15 @@ static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
 	return comp->dev;
 }
 
+static inline
+u32 mtk_ddp_comp_get_blend_modes(struct mtk_ddp_comp *comp)
+{
+	if (comp->funcs && comp->funcs->get_blend_modes)
+		return comp->funcs->get_blend_modes(comp->dev);
+
+	return 0;
+}
+
 static inline
 const u32 *mtk_ddp_comp_get_formats(struct mtk_ddp_comp *comp)
 {
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 082ac18fe04a..04154db9085c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -103,6 +103,7 @@ void mtk_ovl_register_vblank_cb(struct device *dev,
 void mtk_ovl_unregister_vblank_cb(struct device *dev);
 void mtk_ovl_enable_vblank(struct device *dev);
 void mtk_ovl_disable_vblank(struct device *dev);
+u32 mtk_ovl_get_blend_modes(struct device *dev);
 const u32 *mtk_ovl_get_formats(struct device *dev);
 size_t mtk_ovl_get_num_formats(struct device *dev);
 
@@ -131,6 +132,7 @@ void mtk_ovl_adaptor_start(struct device *dev);
 void mtk_ovl_adaptor_stop(struct device *dev);
 unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
 struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev);
+u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev);
 const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
 size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
 enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 0cf7b80f612e..1d3b25d768f9 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -215,6 +215,13 @@ void mtk_ovl_disable_vblank(struct device *dev)
 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
 }
 
+u32 mtk_ovl_get_blend_modes(struct device *dev)
+{
+	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+	return ovl->data->blend_modes;
+}
+
 const u32 *mtk_ovl_get_formats(struct device *dev)
 {
 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index c6768210b08b..bf2546c4681a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -400,6 +400,13 @@ void mtk_ovl_adaptor_disable_vblank(struct device *dev)
 	mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
 }
 
+u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev)
+{
+	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+	return mtk_ethdr_get_blend_modes(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
 const u32 *mtk_ovl_adaptor_get_formats(struct device *dev)
 {
 	struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index d1d9cf8b10e1..0f22e7d337cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -145,6 +145,13 @@ static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+u32 mtk_ethdr_get_blend_modes(struct device *dev)
+{
+	return BIT(DRM_MODE_BLEND_PREMULTI) |
+	       BIT(DRM_MODE_BLEND_COVERAGE) |
+	       BIT(DRM_MODE_BLEND_PIXEL_NONE);
+}
+
 void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 			    struct mtk_plane_state *state,
 			    struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
index 81af9edea3f7..a72aeee46829 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.h
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -13,6 +13,7 @@ void mtk_ethdr_clk_disable(struct device *dev);
 void mtk_ethdr_config(struct device *dev, unsigned int w,
 		      unsigned int h, unsigned int vrefresh,
 		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+u32 mtk_ethdr_get_blend_modes(struct device *dev);
 void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
 			    struct mtk_plane_state *state,
 			    struct cmdq_pkt *cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 7d2cb4e0fafa..8a48b3b0a956 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -320,8 +320,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
 
 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 		   unsigned long possible_crtcs, enum drm_plane_type type,
-		   unsigned int supported_rotations, const u32 *formats,
-		   size_t num_formats, unsigned int plane_idx)
+		   unsigned int supported_rotations, const u32 blend_modes,
+		   const u32 *formats, size_t num_formats, unsigned int plane_idx)
 {
 	int err;
 
@@ -366,12 +366,11 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 	if (err)
 		DRM_ERROR("failed to create property: alpha\n");
 
-	err = drm_plane_create_blend_mode_property(plane,
-						   BIT(DRM_MODE_BLEND_PREMULTI) |
-						   BIT(DRM_MODE_BLEND_COVERAGE) |
-						   BIT(DRM_MODE_BLEND_PIXEL_NONE));
-	if (err)
-		DRM_ERROR("failed to create property: blend_mode\n");
+	if (blend_modes) {
+		err = drm_plane_create_blend_mode_property(plane, blend_modes);
+		if (err)
+			DRM_ERROR("failed to create property: blend_mode\n");
+	}
 
 	drm_plane_helper_add(plane, &mtk_plane_helper_funcs);
 
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.h b/drivers/gpu/drm/mediatek/mtk_plane.h
index 5b177eac67b7..3b13b89989c7 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.h
+++ b/drivers/gpu/drm/mediatek/mtk_plane.h
@@ -48,6 +48,6 @@ to_mtk_plane_state(struct drm_plane_state *state)
 
 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
 		   unsigned long possible_crtcs, enum drm_plane_type type,
-		   unsigned int supported_rotations, const u32 *formats,
-		   size_t num_formats, unsigned int plane_idx);
+		   unsigned int supported_rotations, const u32 blend_modes,
+		   const u32 *formats, size_t num_formats, unsigned int plane_idx);
 #endif
-- 
2.43.0

Re: [PATCH v7 1/3] drm/mediatek: ovl: Remove the color format comment for ovl_fmt_convert()

[CK Hu (胡俊光)]

Hi, Jason:

On Thu, 2024-09-26 at 18:22 +0800, Jason-JH.Lin wrote:
> Since we changed MACROs to be consistent with DRM input color format
> naming, the comment for ovl_fmt_conver() is no longer needed.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Fixes: 9f428b95ac89 ("drm/mediatek: Add new color format MACROs in OVL")
> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 89b439dcf3a6..4a4bc27a67f0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -389,11 +389,6 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
>  static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,
>  				    unsigned int blend_mode)
>  {
> -	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
> -	 * is defined in mediatek HW data sheet.
> -	 * The alphabet order in XXX is no relation to data
> -	 * arrangement in memory.
> -	 */
>  	switch (fmt) {
>  	default:
>  	case DRM_FORMAT_RGB565:

Re: [PATCH v7 0/3] Fix degradation problem of alpha blending series

[Alper Nebi Yasak]

Hi,

On 2024-09-26 13:22 +03:00, Jason-JH.Lin wrote:
> Some SoCs not support pre-multiplied pixel formats and extending
> configuration of OVL pre-multiplied color formats, such as MT8173.
> 
> Fix the SoC degradation problem by this sreies.
> 
> ---
> 
> Change in v7:
> 1. Add the remove color format comment patch for OVL
> 2. Fix warning: 'const' type qualifier on return type has no effect
> 
> [...]

I get warnings and "*ERROR* failed to create property: blend_mode" a few 
times until mediatek-drm initializes. It happens on MT8173 and MT8183, but 
not on MT8186. Colors are correct, though. (I'm tempted to add Tested-by.)

------8<------

From MT8173:

[  +0.017201] ------------[ cut here ]------------
[  +0.009250] WARNING: CPU: 3 PID: 37 at drivers/gpu/drm/drm_blend.c:586 drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[  +0.022533] Modules linked in: [...]
[  +0.158166] CPU: 3 UID: 0 PID: 37 Comm: kworker/u16:1 Tainted: G        W          6.11.0-next-20240927-deb-00006-ge514a0f89dd9 #
[  +0.023542] Tainted: [W]=WARN
[  +0.005936] Hardware name: Google Hana (DT)
[  +0.008379] Workqueue: events_unbound deferred_probe_work_func
[  +0.011694] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[  +0.013959] pc : drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[  +0.013111] lr : mtk_plane_init+0xf4/0x198 [mediatek_drm]
[  +0.010829] sp : ffff800081d538c0
[  +0.006634] x29: ffff800081d538c0 x28: ffff0000c431e080 x27: ffff0000c19787a8
[  +0.014314] x26: 0000000000000548 x25: 0000000000000006 x24: ffff0000c431f000
[  +0.014317] x23: 0000000000000035 x22: 0000000000000006 x21: ffff0000c0ca1058
[  +0.014313] x20: 0000000000000006 x19: 0000000000000000 x18: ffffffffffffffff
[  +0.014314] x17: 6f72702065746165 x16: 7263206f74206465 x15: ffff0000c414e626
[  +0.014316] x14: 0000000000000000 x13: 0000000000000028 x12: 0101010101010101
[  +0.014313] x11: 7f7f7f7f7f7f7f7f x10: fefefeff726e6f79 x9 : ffff800079e689dc
[  +0.014316] x8 : ffff0000c5875554 x7 : 00000000eeeeeeee x6 : 00000000c0c0c0c0
[  +0.014314] x5 : 0000000000000000 x4 : ffff0000c0ca1190 x3 : ffff0000c0ca1190
[  +0.014313] x2 : 000000000000ffff x1 : 0000000000000006 x0 : ffff0000c0ca1058
[  +0.014314] Call trace:
[  +0.004891]  drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[  +0.012415]  mtk_plane_init+0xf4/0x198 [mediatek_drm]
[  +0.010132]  mtk_crtc_create+0x34c/0x858 [mediatek_drm]
[  +0.010479]  mtk_drm_bind+0x4b4/0x600 [mediatek_drm]
[  +0.009956]  try_to_bring_up_aggregate_device+0x21c/0x2e8
[  +0.010825]  __component_add+0xc0/0x1c0
[  +0.007685]  component_add+0x1c/0x38
[  +0.007163]  mtk_disp_rdma_probe+0x148/0x230 [mediatek_drm]
[  +0.011175]  platform_probe+0x70/0xe8
[  +0.007338]  really_probe+0xc8/0x3a0
[  +0.007161]  __driver_probe_device+0x84/0x160
[  +0.008730]  driver_probe_device+0x44/0x130
[  +0.008379]  __device_attach_driver+0xc4/0x170
[  +0.008905]  bus_for_each_drv+0x90/0x100
[  +0.007855]  __device_attach+0xa8/0x1c8
[  +0.007685]  device_initial_probe+0x1c/0x30
[  +0.008380]  bus_probe_device+0xb0/0xc0
[  +0.007683]  deferred_probe_work_func+0xbc/0x120
[  +0.009253]  process_one_work+0x178/0x3d0
[  +0.008033]  worker_thread+0x200/0x3f0
[  +0.007511]  kthread+0xe8/0xf8
[  +0.006115]  ret_from_fork+0x10/0x20
[  +0.007164] ---[ end trace 0000000000000000 ]---
[  +0.009278] [drm:mtk_plane_init [mediatek_drm]] *ERROR* failed to create property: blend_mode

From MT8183:

[   13.936989] ------------[ cut here ]------------
[   13.946224] WARNING: CPU: 5 PID: 60 at drivers/gpu/drm/drm_blend.c:586 drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[   13.968714] Modules linked in: [...]
[   14.116814] CPU: 5 UID: 0 PID: 60 Comm: kworker/u34:2 Tainted: G        W          6.11.0-next-20240927-deb-00006-ge514a0f89dd9 #1
[   14.140323] Tainted: [W]=WARN
[   14.146248] Hardware name: Google cozmo board (DT)
[   14.155830] Workqueue: events_unbound deferred_probe_work_func
[   14.167505] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[   14.181440] pc : drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[   14.194529] lr : mtk_plane_init+0xf4/0x188 [mediatek_drm]
[   14.205338] sp : ffff8000804a3860
[   14.211960] x29: ffff8000804a3860 x28: ffff715445288080 x27: ffff7154417fa748
[   14.226247] x26: 0000000000000548 x25: 0000000000000006 x24: ffff71544528a000
[   14.240536] x23: 0000000000000035 x22: 0000000000000006 x21: ffff715445a49ae8
[   14.254822] x20: 0000000000000006 x19: 0000000000000000 x18: ffffffffffffffff
[   14.269110] x17: 6f72702065746165 x16: ffffd6facceae8c0 x15: ffff715470421d46
[   14.283398] x14: 0000000000000000 x13: 0000000000000028 x12: 0101010101010101
[   14.297686] x11: 7f7f7f7f7f7f7f7f x10: fefefeff726e6f79 x9 : ffffd6fa92d179dc
[   14.311973] x8 : ffff715445156ad4 x7 : 00000000eeeeeeee x6 : 00000000c0c0c0c0
[   14.326261] x5 : 0000000000000000 x4 : ffff715445a49c20 x3 : ffff715445a49c20
[   14.340549] x2 : 000000000000ffff x1 : 0000000000000006 x0 : ffff715445a49ae8
[   14.354837] Call trace:
[   14.359718]  drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
[   14.372111]  mtk_plane_init+0xf4/0x188 [mediatek_drm]
[   14.382224]  mtk_crtc_create+0x34c/0x858 [mediatek_drm]
[   14.392685]  mtk_drm_bind+0x51c/0x600 [mediatek_drm]
[   14.402622]  try_to_bring_up_aggregate_device+0x21c/0x2e8
[   14.413425]  __component_add+0xc0/0x1c0
[   14.421094]  component_add+0x1c/0x38
[   14.428241]  mtk_dsi_host_attach+0x80/0xe0 [mediatek_drm]
[   14.439049]  devm_mipi_dsi_attach+0x3c/0xa0
[   14.447413]  anx7625_link_bridge+0xfc/0x1c8 [anx7625]
[   14.457522]  dp_aux_ep_probe+0x54/0x110 [drm_dp_aux_bus]
[   14.468150]  really_probe+0xc8/0x3a0
[   14.475296]  __driver_probe_device+0x84/0x160
[   14.484009]  driver_probe_device+0x44/0x130
[   14.492374]  __device_attach_driver+0xc4/0x170
[   14.501261]  bus_for_each_drv+0x90/0x100
[   14.509103]  __device_attach+0xa8/0x1c8
[   14.516772]  device_initial_probe+0x1c/0x30
[   14.525137]  bus_probe_device+0xb0/0xc0
[   14.532805]  deferred_probe_work_func+0xbc/0x120
[   14.542040]  process_one_work+0x178/0x3d0
[   14.550059]  worker_thread+0x200/0x3f0
[   14.557553]  kthread+0xe8/0xf8
[   14.563656]  ret_from_fork+0x10/0x20
[   14.570803] ---[ end trace 0000000000000000 ]---
[   14.580052] [drm:mtk_plane_init [mediatek_drm]] *ERROR* failed to create property: blend_mode

Re: [PATCH v7 0/3] Fix degradation problem of alpha blending series

[Jason-JH Lin (林睿祥)]

Hi Alper,

On Sat, 2024-09-28 at 16:02 +0300, Alper Nebi Yasak wrote:
>  	 
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Hi,
> 
> On 2024-09-26 13:22 +03:00, Jason-JH.Lin wrote:
> > Some SoCs not support pre-multiplied pixel formats and extending
> > configuration of OVL pre-multiplied color formats, such as MT8173.
> > 
> > Fix the SoC degradation problem by this sreies.
> > 
> > ---
> > 
> > Change in v7:
> > 1. Add the remove color format comment patch for OVL
> > 2. Fix warning: 'const' type qualifier on return type has no effect
> > 
> > [...]
> 
> I get warnings and "*ERROR* failed to create property: blend_mode" a
> few 
> times until mediatek-drm initializes. It happens on MT8173 and
> MT8183, but 
> not on MT8186. Colors are correct, though. (I'm tempted to add
> Tested-by.)
> 

MT8186 is using MT8192's compatible name, so its blend_modes suppots
pre-multiplied.

> ------8<------
> 
> From MT8173:
> 
> [  +0.017201] ------------[ cut here ]------------
> [  +0.009250] WARNING: CPU: 3 PID: 37 at
> drivers/gpu/drm/drm_blend.c:586
> drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
> [  +0.022533] Modules linked in: [...]
> [  +0.158166] CPU: 3 UID: 0 PID: 37 Comm: kworker/u16:1 Tainted:
> G        W          6.11.0-next-20240927-deb-00006-ge514a0f89dd9 #
> [  +0.023542] Tainted: [W]=WARN
> [  +0.005936] Hardware name: Google Hana (DT)
> [  +0.008379] Workqueue: events_unbound deferred_probe_work_func
> [  +0.011694] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS
> BTYPE=--)
> [  +0.013959] pc : drm_plane_create_blend_mode_property+0xf0/0x110
> [drm]
> [  +0.013111] lr : mtk_plane_init+0xf4/0x198 [mediatek_drm]
> [  +0.010829] sp : ffff800081d538c0
> [  +0.006634] x29: ffff800081d538c0 x28: ffff0000c431e080 x27:
> ffff0000c19787a8
> [  +0.014314] x26: 0000000000000548 x25: 0000000000000006 x24:
> ffff0000c431f000
> [  +0.014317] x23: 0000000000000035 x22: 0000000000000006 x21:
> ffff0000c0ca1058
> [  +0.014313] x20: 0000000000000006 x19: 0000000000000000 x18:
> ffffffffffffffff
> [  +0.014314] x17: 6f72702065746165 x16: 7263206f74206465 x15:
> ffff0000c414e626
> [  +0.014316] x14: 0000000000000000 x13: 0000000000000028 x12:
> 0101010101010101
> [  +0.014313] x11: 7f7f7f7f7f7f7f7f x10: fefefeff726e6f79 x9 :
> ffff800079e689dc
> [  +0.014316] x8 : ffff0000c5875554 x7 : 00000000eeeeeeee x6 :
> 00000000c0c0c0c0
> [  +0.014314] x5 : 0000000000000000 x4 : ffff0000c0ca1190 x3 :
> ffff0000c0ca1190
> [  +0.014313] x2 : 000000000000ffff x1 : 0000000000000006 x0 :
> ffff0000c0ca1058
> [  +0.014314] Call trace:
> [  +0.004891]  drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
> [  +0.012415]  mtk_plane_init+0xf4/0x198 [mediatek_drm]
> [  +0.010132]  mtk_crtc_create+0x34c/0x858 [mediatek_drm]
> [  +0.010479]  mtk_drm_bind+0x4b4/0x600 [mediatek_drm]
> [  +0.009956]  try_to_bring_up_aggregate_device+0x21c/0x2e8
> [  +0.010825]  __component_add+0xc0/0x1c0
> [  +0.007685]  component_add+0x1c/0x38
> [  +0.007163]  mtk_disp_rdma_probe+0x148/0x230 [mediatek_drm]
> [  +0.011175]  platform_probe+0x70/0xe8
> [  +0.007338]  really_probe+0xc8/0x3a0
> [  +0.007161]  __driver_probe_device+0x84/0x160
> [  +0.008730]  driver_probe_device+0x44/0x130
> [  +0.008379]  __device_attach_driver+0xc4/0x170
> [  +0.008905]  bus_for_each_drv+0x90/0x100
> [  +0.007855]  __device_attach+0xa8/0x1c8
> [  +0.007685]  device_initial_probe+0x1c/0x30
> [  +0.008380]  bus_probe_device+0xb0/0xc0
> [  +0.007683]  deferred_probe_work_func+0xbc/0x120
> [  +0.009253]  process_one_work+0x178/0x3d0
> [  +0.008033]  worker_thread+0x200/0x3f0
> [  +0.007511]  kthread+0xe8/0xf8
> [  +0.006115]  ret_from_fork+0x10/0x20
> [  +0.007164] ---[ end trace 0000000000000000 ]---
> [  +0.009278] [drm:mtk_plane_init [mediatek_drm]] *ERROR* failed to
> create property: blend_mode
> 
> From MT8183:
> 
> [   13.936989] ------------[ cut here ]------------
> [   13.946224] WARNING: CPU: 5 PID: 60 at
> drivers/gpu/drm/drm_blend.c:586
> drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
> [   13.968714] Modules linked in: [...]
> [   14.116814] CPU: 5 UID: 0 PID: 60 Comm: kworker/u34:2 Tainted:
> G        W          6.11.0-next-20240927-deb-00006-ge514a0f89dd9 #1
> [   14.140323] Tainted: [W]=WARN
> [   14.146248] Hardware name: Google cozmo board (DT)
> [   14.155830] Workqueue: events_unbound deferred_probe_work_func
> [   14.167505] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS
> BTYPE=--)
> [   14.181440] pc : drm_plane_create_blend_mode_property+0xf0/0x110
> [drm]
> [   14.194529] lr : mtk_plane_init+0xf4/0x188 [mediatek_drm]
> [   14.205338] sp : ffff8000804a3860
> [   14.211960] x29: ffff8000804a3860 x28: ffff715445288080 x27:
> ffff7154417fa748
> [   14.226247] x26: 0000000000000548 x25: 0000000000000006 x24:
> ffff71544528a000
> [   14.240536] x23: 0000000000000035 x22: 0000000000000006 x21:
> ffff715445a49ae8
> [   14.254822] x20: 0000000000000006 x19: 0000000000000000 x18:
> ffffffffffffffff
> [   14.269110] x17: 6f72702065746165 x16: ffffd6facceae8c0 x15:
> ffff715470421d46
> [   14.283398] x14: 0000000000000000 x13: 0000000000000028 x12:
> 0101010101010101
> [   14.297686] x11: 7f7f7f7f7f7f7f7f x10: fefefeff726e6f79 x9 :
> ffffd6fa92d179dc
> [   14.311973] x8 : ffff715445156ad4 x7 : 00000000eeeeeeee x6 :
> 00000000c0c0c0c0
> [   14.326261] x5 : 0000000000000000 x4 : ffff715445a49c20 x3 :
> ffff715445a49c20
> [   14.340549] x2 : 000000000000ffff x1 : 0000000000000006 x0 :
> ffff715445a49ae8
> [   14.354837] Call trace:
> [   14.359718]  drm_plane_create_blend_mode_property+0xf0/0x110 [drm]
> [   14.372111]  mtk_plane_init+0xf4/0x188 [mediatek_drm]
> [   14.382224]  mtk_crtc_create+0x34c/0x858 [mediatek_drm]
> [   14.392685]  mtk_drm_bind+0x51c/0x600 [mediatek_drm]
> [   14.402622]  try_to_bring_up_aggregate_device+0x21c/0x2e8
> [   14.413425]  __component_add+0xc0/0x1c0
> [   14.421094]  component_add+0x1c/0x38
> [   14.428241]  mtk_dsi_host_attach+0x80/0xe0 [mediatek_drm]
> [   14.439049]  devm_mipi_dsi_attach+0x3c/0xa0
> [   14.447413]  anx7625_link_bridge+0xfc/0x1c8 [anx7625]
> [   14.457522]  dp_aux_ep_probe+0x54/0x110 [drm_dp_aux_bus]
> [   14.468150]  really_probe+0xc8/0x3a0
> [   14.475296]  __driver_probe_device+0x84/0x160
> [   14.484009]  driver_probe_device+0x44/0x130
> [   14.492374]  __device_attach_driver+0xc4/0x170
> [   14.501261]  bus_for_each_drv+0x90/0x100
> [   14.509103]  __device_attach+0xa8/0x1c8
> [   14.516772]  device_initial_probe+0x1c/0x30
> [   14.525137]  bus_probe_device+0xb0/0xc0
> [   14.532805]  deferred_probe_work_func+0xbc/0x120
> [   14.542040]  process_one_work+0x178/0x3d0
> [   14.550059]  worker_thread+0x200/0x3f0
> [   14.557553]  kthread+0xe8/0xf8
> [   14.563656]  ret_from_fork+0x10/0x20
> [   14.570803] ---[ end trace 0000000000000000 ]---
> [   14.580052] [drm:mtk_plane_init [mediatek_drm]] *ERROR* failed to
> create property: blend_mode

Take a glimpse of drm_plane_create_blend_mode_property(), it can simply
find the reason here:
/**
 * drm_plane_create_blend_mode_property - create a new blend mode
property
 * @plane: drm plane
 * @supported_modes: bitmask of supported modes, must include
 *           BIT(DRM_MODE_BLEND_PREMULTI). Current DRM assumption is
 *           that alpha is premultiplied, and old userspace can break
if
 *           the property defaults to anything else.
 ...
 * RETURNS:
 * Zero for success or -errno
 */

int drm_plane_create_blend_mode_property(struct drm_plane *plane,
                     unsigned int supported_modes)
{
    unsigned int valid_mode_mask = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
                                   BIT(DRM_MODE_BLEND_PREMULTI)   |
                                   BIT(DRM_MODE_BLEND_COVERAGE);
...

    if (WARN_ON((supported_modes & ~valid_mode_mask) ||
        ((supported_modes & BIT(DRM_MODE_BLEND_PREMULTI)) == 0)))
        return -EINVAL;
...
}

So I think if the SoCs don't support pre-multiplied color formats, then
just not create the blend_mode property and use the coverage mode color
format as default settings for OVL.

I'll send v8 for this.

Thanks for the verification on MT8173, MT8183 and MT8186.

Regards,
Jason-JH.Lin