From: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
To: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips
Date: Mon, 31 Aug 2020 12:55:16 +0200 [thread overview]
Message-ID: <ae094597-e57e-dff1-f897-bf3cc75f5511@prevas.dk> (raw)
In-Reply-To: <20200812151818.16699-3-i.mikhaylov@yadro.com>
On 12/08/2020 17.18, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
>
> Tested with mx25l51245g(BP0-3).
Hmm. I've tried adding support for locking on Macronix to U-Boot
(https://patchwork.ozlabs.org/project/uboot/patch/20200326114257.1782-3-rasmus.villemoes@prevas.dk/),
but that was quite a bit more involved than this. Note in particular the
first part of my commit message:
Macronix chips implements locking in (power-of-two multiple of) 64K
blocks, not as a fraction of the chip's size.
At least, that was true for the chip I was interested in and the few
others whose data sheets I grabbed to double-check. So I'm a bit
skeptical that this can work out-of-the-box without introducing a new
struct spi_nor_locking_ops.
Rasmus
next prev parent reply other threads:[~2020-08-31 10:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-12 15:18 [PATCH 0/2] " Ivan Mikhaylov
2020-08-12 15:18 ` [PATCH 1/2] mtd: spi-nor: do not touch TB bit without SPI_NOR_HAS_TB Ivan Mikhaylov
2020-08-12 15:18 ` [PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips Ivan Mikhaylov
2020-08-31 10:55 ` Rasmus Villemoes [this message]
2020-09-01 14:06 ` Ivan Mikhaylov
2020-08-31 10:38 ` [PATCH 0/2] " Ivan Mikhaylov
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