[RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Jose Javier Rodriguez Barbarin]

This series is an RFC for adding port-mapped I/O (PMIO) support to
gpio-mmio.

This v2 comes with all suggestions done by Linux Walleij in the
initial review [1].

For keeping compatibility with gpio_generic_chip, a new _config struct
was added instead of extending gpio_generic_chip_config. Using such new
_config struct, called gpio_generic_chip_port_config, requires a new API
function gpio_generic_chip_port_init() to access to that new structure.

Besides, structure gpio_chip_reg has been transformed to union. It reflects
better that MMIO and PMIO chips will only use one of them, saving memory
as well.

I'm still sending this as RFC but I don't know if I should send this as a
regular PATCH series.

[1] https://lore.kernel.org/linux-gpio/20260407184805.807328-1-dev-josejavier.rodriguez@duagon.com

---
Changes in v2:
    - Move struct gpio_chip_reg to union gpio_chip_reg.
    - Add a new gpio-mmio API function to init PMIO generic chips.

Jose Javier Rodriguez Barbarin (3):
  gpio: mmio: convert accessors to generic register descriptors
  gpio: mmio: add port-mapped read/write callbacks
  gpio: mmio: add port-mapped support for gpio_generic_chip

 drivers/gpio/gpio-mmio.c     | 330 ++++++++++++++++++++++++-----------
 include/linux/gpio/generic.h |  78 ++++++++-
 2 files changed, 300 insertions(+), 108 deletions(-)

-- 
2.53.0

[RFC PATCH v2 1/3] gpio: mmio: convert accessors to generic register descriptors

[Jose Javier Rodriguez Barbarin]

Convert the gpio-mmio accessors to use union gpio_chip_reg instead of
the previous MMIO-only register type.

This allows the same accessors to operate on both MMIO and PMIO
registers and aligns gpio-mmio with the updated gpio_generic_chip API.

Move the initialization code shared by MMIO and PMIO devices to a new
function gpio_generic_chip_init_common(), leaving gpio_generic_chip_init()
with the MMIO-specific initialization.

Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>
---
 drivers/gpio/gpio-mmio.c     | 208 ++++++++++++++++++-----------------
 include/linux/gpio/generic.h |  37 +++++--
 2 files changed, 138 insertions(+), 107 deletions(-)

diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c
index edbcaad57d00..39326ab7e494 100644
--- a/drivers/gpio/gpio-mmio.c
+++ b/drivers/gpio/gpio-mmio.c
@@ -62,66 +62,71 @@ o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
 
 #include "gpiolib.h"
 
-static void gpio_mmio_write8(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write8(union gpio_chip_reg *reg, unsigned long data)
 {
-	writeb(data, reg);
+	writeb(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read8(void __iomem *reg)
+static unsigned long gpio_mmio_read8(union gpio_chip_reg *reg)
 {
-	return readb(reg);
+	return readb(reg->mmio);
 }
 
-static void gpio_mmio_write16(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write16(union gpio_chip_reg *reg, unsigned long data)
 {
-	writew(data, reg);
+	writew(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read16(void __iomem *reg)
+static unsigned long gpio_mmio_read16(union gpio_chip_reg *reg)
 {
-	return readw(reg);
+	return readw(reg->mmio);
 }
 
-static void gpio_mmio_write32(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write32(union gpio_chip_reg *reg, unsigned long data)
 {
-	writel(data, reg);
+	writel(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read32(void __iomem *reg)
+static unsigned long gpio_mmio_read32(union gpio_chip_reg *reg)
 {
-	return readl(reg);
+	return readl(reg->mmio);
 }
 
 #if BITS_PER_LONG >= 64
-static void gpio_mmio_write64(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write64(union gpio_chip_reg *reg, unsigned long data)
 {
-	writeq(data, reg);
+	writeq(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read64(void __iomem *reg)
+static unsigned long gpio_mmio_read64(union gpio_chip_reg *reg)
 {
-	return readq(reg);
+	return readq(reg->mmio);
 }
 #endif /* BITS_PER_LONG >= 64 */
 
-static void gpio_mmio_write16be(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write16be(union gpio_chip_reg *reg, unsigned long data)
 {
-	iowrite16be(data, reg);
+	iowrite16be(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read16be(void __iomem *reg)
+static unsigned long gpio_mmio_read16be(union gpio_chip_reg *reg)
 {
-	return ioread16be(reg);
+	return ioread16be(reg->mmio);
 }
 
-static void gpio_mmio_write32be(void __iomem *reg, unsigned long data)
+static void gpio_mmio_write32be(union gpio_chip_reg *reg, unsigned long data)
 {
-	iowrite32be(data, reg);
+	iowrite32be(data, reg->mmio);
 }
 
-static unsigned long gpio_mmio_read32be(void __iomem *reg)
+static unsigned long gpio_mmio_read32be(union gpio_chip_reg *reg)
 {
-	return ioread32be(reg);
+	return ioread32be(reg->mmio);
+}
+
+static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg)
+{
+	return reg->port != 0;
 }
 
 static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line)
@@ -140,9 +145,9 @@ static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio)
 	bool dir = !!(chip->sdir & pinmask);
 
 	if (dir)
-		return !!(chip->read_reg(chip->reg_set) & pinmask);
+		return !!(chip->read_reg(&chip->reg_set) & pinmask);
 
-	return !!(chip->read_reg(chip->reg_dat) & pinmask);
+	return !!(chip->read_reg(&chip->reg_dat) & pinmask);
 }
 
 /*
@@ -162,9 +167,9 @@ static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 	get_mask = *mask & ~chip->sdir;
 
 	if (set_mask)
-		*bits |= chip->read_reg(chip->reg_set) & set_mask;
+		*bits |= chip->read_reg(&chip->reg_set) & set_mask;
 	if (get_mask)
-		*bits |= chip->read_reg(chip->reg_dat) & get_mask;
+		*bits |= chip->read_reg(&chip->reg_dat) & get_mask;
 
 	return 0;
 }
@@ -173,7 +178,7 @@ static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio)
 {
 	struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
 
-	return !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));
+	return !!(chip->read_reg(&chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));
 }
 
 /*
@@ -186,7 +191,7 @@ static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
 
 	/* Make sure we first clear any bits that are zero when we read the register */
 	*bits &= ~*mask;
-	*bits |= chip->read_reg(chip->reg_dat) & *mask;
+	*bits |= chip->read_reg(&chip->reg_dat) & *mask;
 	return 0;
 }
 
@@ -209,7 +214,7 @@ static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
 		readmask |= gpio_mmio_line2mask(gc, bit);
 
 	/* Read the register */
-	val = chip->read_reg(chip->reg_dat) & readmask;
+	val = chip->read_reg(&chip->reg_dat) & readmask;
 
 	/*
 	 * Mirror the result into the "bits" result, this will give line 0
@@ -238,7 +243,7 @@ static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 	else
 		chip->sdata &= ~mask;
 
-	chip->write_reg(chip->reg_dat, chip->sdata);
+	chip->write_reg(&chip->reg_dat, chip->sdata);
 
 	return 0;
 }
@@ -250,9 +255,9 @@ static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
 	unsigned long mask = gpio_mmio_line2mask(gc, gpio);
 
 	if (val)
-		chip->write_reg(chip->reg_set, mask);
+		chip->write_reg(&chip->reg_set, mask);
 	else
-		chip->write_reg(chip->reg_clr, mask);
+		chip->write_reg(&chip->reg_clr, mask);
 
 	return 0;
 }
@@ -269,7 +274,7 @@ static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
 	else
 		chip->sdata &= ~mask;
 
-	chip->write_reg(chip->reg_set, chip->sdata);
+	chip->write_reg(&chip->reg_set, chip->sdata);
 
 	return 0;
 }
@@ -297,7 +302,7 @@ static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc,
 static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc,
 					      unsigned long *mask,
 					      unsigned long *bits,
-					      void __iomem *reg)
+					      union gpio_chip_reg *reg)
 {
 	struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
 	unsigned long set_mask, clear_mask;
@@ -317,7 +322,7 @@ static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
 {
 	struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
 
-	gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat);
+	gpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_dat);
 
 	return 0;
 }
@@ -327,7 +332,7 @@ static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
 {
 	struct gpio_generic_chip *chip = to_gpio_generic_chip(gc);
 
-	gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set);
+	gpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_set);
 
 	return 0;
 }
@@ -342,9 +347,9 @@ static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc,
 	gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
 
 	if (set_mask)
-		chip->write_reg(chip->reg_set, set_mask);
+		chip->write_reg(&chip->reg_set, set_mask);
 	if (clear_mask)
-		chip->write_reg(chip->reg_clr, clear_mask);
+		chip->write_reg(&chip->reg_clr, clear_mask);
 
 	return 0;
 }
@@ -394,10 +399,10 @@ static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio)
 	scoped_guard(raw_spinlock_irqsave, &chip->lock) {
 		chip->sdir &= ~gpio_mmio_line2mask(gc, gpio);
 
-		if (chip->reg_dir_in)
-			chip->write_reg(chip->reg_dir_in, ~chip->sdir);
-		if (chip->reg_dir_out)
-			chip->write_reg(chip->reg_dir_out, chip->sdir);
+		if (gpio_chip_reg_is_set(&chip->reg_dir_in))
+			chip->write_reg(&chip->reg_dir_in, ~chip->sdir);
+		if (gpio_chip_reg_is_set(&chip->reg_dir_out))
+			chip->write_reg(&chip->reg_dir_out, chip->sdir);
 	}
 
 	return gpio_mmio_dir_return(gc, gpio, false);
@@ -414,14 +419,14 @@ static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio)
 		return GPIO_LINE_DIRECTION_IN;
 	}
 
-	if (chip->reg_dir_out) {
-		if (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))
+	if (gpio_chip_reg_is_set(&chip->reg_dir_out)) {
+		if (chip->read_reg(&chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))
 			return GPIO_LINE_DIRECTION_OUT;
 		return GPIO_LINE_DIRECTION_IN;
 	}
 
-	if (chip->reg_dir_in)
-		if (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))
+	if (gpio_chip_reg_is_set(&chip->reg_dir_in))
+		if (!(chip->read_reg(&chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))
 			return GPIO_LINE_DIRECTION_OUT;
 
 	return GPIO_LINE_DIRECTION_IN;
@@ -435,10 +440,10 @@ static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 
 	chip->sdir |= gpio_mmio_line2mask(gc, gpio);
 
-	if (chip->reg_dir_in)
-		chip->write_reg(chip->reg_dir_in, ~chip->sdir);
-	if (chip->reg_dir_out)
-		chip->write_reg(chip->reg_dir_out, chip->sdir);
+	if (gpio_chip_reg_is_set(&chip->reg_dir_in))
+		chip->write_reg(&chip->reg_dir_in, ~chip->sdir);
+	if (gpio_chip_reg_is_set(&chip->reg_dir_out))
+		chip->write_reg(&chip->reg_dir_out, chip->sdir);
 }
 
 static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
@@ -526,25 +531,22 @@ static int gpio_mmio_setup_accessors(struct device *dev,
  *	- an input direction register (named "dirin") where a 1 bit indicates
  *	the GPIO is an input.
  */
-static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,
-			      const struct gpio_generic_chip_config *cfg)
+static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, int flags)
 {
 	struct gpio_chip *gc = &chip->gc;
 
-	chip->reg_dat = cfg->dat;
-	if (!chip->reg_dat)
+	if (!gpio_chip_reg_is_set(&chip->reg_dat))
 		return -EINVAL;
 
-	if (cfg->set && cfg->clr) {
-		chip->reg_set = cfg->set;
-		chip->reg_clr = cfg->clr;
+	if (gpio_chip_reg_is_set(&chip->reg_set) &&
+	    gpio_chip_reg_is_set(&chip->reg_clr)) {
 		gc->set = gpio_mmio_set_with_clear;
 		gc->set_multiple = gpio_mmio_set_multiple_with_clear;
-	} else if (cfg->set && !cfg->clr) {
-		chip->reg_set = cfg->set;
+	} else if (gpio_chip_reg_is_set(&chip->reg_set) &&
+		   !gpio_chip_reg_is_set(&chip->reg_clr)) {
 		gc->set = gpio_mmio_set_set;
 		gc->set_multiple = gpio_mmio_set_multiple_set;
-	} else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) {
+	} else if (flags & GPIO_GENERIC_NO_OUTPUT) {
 		gc->set = gpio_mmio_set_none;
 		gc->set_multiple = NULL;
 	} else {
@@ -552,8 +554,8 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,
 		gc->set_multiple = gpio_mmio_set_multiple;
 	}
 
-	if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) &&
-	    (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) {
+	if (!(flags & GPIO_GENERIC_UNREADABLE_REG_SET) &&
+	    (flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) {
 		gc->get = gpio_mmio_get_set;
 		if (!chip->be_bits)
 			gc->get_multiple = gpio_mmio_get_set_multiple;
@@ -575,27 +577,24 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,
 	return 0;
 }
 
-static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip,
-				     const struct gpio_generic_chip_config *cfg)
+static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, int flags)
 {
 	struct gpio_chip *gc = &chip->gc;
-
-	if (cfg->dirout || cfg->dirin) {
-		chip->reg_dir_out = cfg->dirout;
-		chip->reg_dir_in = cfg->dirin;
-		if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT)
+	if (gpio_chip_reg_is_set(&chip->reg_dir_out) ||
+		gpio_chip_reg_is_set(&chip->reg_dir_in)) {
+		if (flags & GPIO_GENERIC_NO_SET_ON_INPUT)
 			gc->direction_output = gpio_mmio_dir_out_dir_first;
 		else
 			gc->direction_output = gpio_mmio_dir_out_val_first;
 		gc->direction_input = gpio_mmio_dir_in;
 		gc->get_direction = gpio_mmio_get_dir;
 	} else {
-		if (cfg->flags & GPIO_GENERIC_NO_OUTPUT)
+		if (flags & GPIO_GENERIC_NO_OUTPUT)
 			gc->direction_output = gpio_mmio_dir_out_err;
 		else
 			gc->direction_output = gpio_mmio_simple_dir_out;
 
-		if (cfg->flags & GPIO_GENERIC_NO_INPUT)
+		if (flags & GPIO_GENERIC_NO_INPUT)
 			gc->direction_input = gpio_mmio_dir_in_err;
 		else
 			gc->direction_input = gpio_mmio_simple_dir_in;
@@ -617,25 +616,18 @@ static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin)
 	return 0;
 }
 
-/**
- * gpio_generic_chip_init() - Initialize a generic GPIO chip.
- * @chip: Generic GPIO chip to set up.
- * @cfg: Generic GPIO chip configuration.
- *
- * Returns 0 on success, negative error number on failure.
- */
-int gpio_generic_chip_init(struct gpio_generic_chip *chip,
-			   const struct gpio_generic_chip_config *cfg)
+static int gpio_generic_chip_init_common(struct gpio_generic_chip *chip,
+					int sz,
+					int flags,
+					struct device *dev)
 {
 	struct gpio_chip *gc = &chip->gc;
-	unsigned long flags = cfg->flags;
-	struct device *dev = cfg->dev;
 	int ret;
 
-	if (!is_power_of_2(cfg->sz))
+	if (!is_power_of_2(sz))
 		return -EINVAL;
 
-	chip->bits = cfg->sz * 8;
+	chip->bits = sz * 8;
 	if (chip->bits > BITS_PER_LONG)
 		return -EINVAL;
 
@@ -650,16 +642,16 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,
 	if (ret)
 		gc->ngpio = chip->bits;
 
-	ret = gpio_mmio_setup_io(chip, cfg);
+	ret = gpio_mmio_setup_io(chip, flags);
 	if (ret)
 		return ret;
 
 	ret = gpio_mmio_setup_accessors(dev, chip,
-				    flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
+				flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
 	if (ret)
 		return ret;
 
-	ret = gpio_mmio_setup_direction(chip, cfg);
+	ret = gpio_mmio_setup_direction(chip, flags);
 	if (ret)
 		return ret;
 
@@ -669,10 +661,10 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,
 		gc->free = gpiochip_generic_free;
 	}
 
-	chip->sdata = chip->read_reg(chip->reg_dat);
+	chip->sdata = chip->read_reg(&chip->reg_dat);
 	if (gc->set == gpio_mmio_set_set &&
 			!(flags & GPIO_GENERIC_UNREADABLE_REG_SET))
-		chip->sdata = chip->read_reg(chip->reg_set);
+		chip->sdata = chip->read_reg(&chip->reg_set);
 
 	if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR)
 		chip->dir_unreadable = true;
@@ -680,24 +672,44 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,
 	/*
 	 * Inspect hardware to find initial direction setting.
 	 */
-	if ((chip->reg_dir_out || chip->reg_dir_in) &&
+	if ((gpio_chip_reg_is_set(&chip->reg_dir_out) || gpio_chip_reg_is_set(&chip->reg_dir_in)) &&
 	    !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) {
-		if (chip->reg_dir_out)
-			chip->sdir = chip->read_reg(chip->reg_dir_out);
-		else if (chip->reg_dir_in)
-			chip->sdir = ~chip->read_reg(chip->reg_dir_in);
+		if (gpio_chip_reg_is_set(&chip->reg_dir_out))
+			chip->sdir = chip->read_reg(&chip->reg_dir_out);
+		else if (gpio_chip_reg_is_set(&chip->reg_dir_in))
+			chip->sdir = ~chip->read_reg(&chip->reg_dir_in);
 		/*
 		 * If we have two direction registers, synchronise
 		 * input setting to output setting, the library
 		 * can not handle a line being input and output at
 		 * the same time.
 		 */
-		if (chip->reg_dir_out && chip->reg_dir_in)
-			chip->write_reg(chip->reg_dir_in, ~chip->sdir);
+		if (gpio_chip_reg_is_set(&chip->reg_dir_out) &&
+		    gpio_chip_reg_is_set(&chip->reg_dir_in))
+			chip->write_reg(&chip->reg_dir_in, ~chip->sdir);
 	}
 
 	return ret;
 }
+
+/**
+ * gpio_generic_chip_init() - Initialize a generic GPIO chip
+ * @chip: Generic GPIO chip to set up.
+ * @cfg: Generic GPIO chip configuration.
+ *
+ * Returns 0 on success, negative error number on failure.
+ */
+int gpio_generic_chip_init(struct gpio_generic_chip *chip,
+			   const struct gpio_generic_chip_config *cfg)
+{
+	chip->reg_dat.mmio = cfg->dat;
+	chip->reg_set.mmio = cfg->set;
+	chip->reg_clr.mmio = cfg->clr;
+	chip->reg_dir_in.mmio = cfg->dirin;
+	chip->reg_dir_out.mmio = cfg->dirout;
+
+	return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);
+}
 EXPORT_SYMBOL_GPL(gpio_generic_chip_init);
 
 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h
index ff566dc9c3cb..30f0d87422e9 100644
--- a/include/linux/gpio/generic.h
+++ b/include/linux/gpio/generic.h
@@ -56,6 +56,19 @@ struct gpio_generic_chip_config {
 	unsigned long flags;
 };
 
+/**
+ * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or port-mapped I/O
+ * @mmio: MMIO register address.
+ * @port: I/O Port register address.
+ *
+ * Describes a GPIO chip register located either in MMIO space or in
+ * port-mapped I/O space.
+ */
+union gpio_chip_reg {
+	void __iomem *mmio;
+	unsigned long port;
+};
+
 /**
  * struct gpio_generic_chip - Generic GPIO chip implementation.
  * @gc: The underlying struct gpio_chip object, implementing low-level GPIO
@@ -84,14 +97,14 @@ struct gpio_generic_chip_config {
  */
 struct gpio_generic_chip {
 	struct gpio_chip gc;
-	unsigned long (*read_reg)(void __iomem *reg);
-	void (*write_reg)(void __iomem *reg, unsigned long data);
+	unsigned long (*read_reg)(union gpio_chip_reg *reg);
+	void (*write_reg)(union gpio_chip_reg *reg, unsigned long data);
 	bool be_bits;
-	void __iomem *reg_dat;
-	void __iomem *reg_set;
-	void __iomem *reg_clr;
-	void __iomem *reg_dir_out;
-	void __iomem *reg_dir_in;
+	union gpio_chip_reg reg_dat;
+	union gpio_chip_reg reg_set;
+	union gpio_chip_reg reg_clr;
+	union gpio_chip_reg reg_dir_out;
+	union gpio_chip_reg reg_dir_in;
 	bool dir_unreadable;
 	bool pinctrl;
 	int bits;
@@ -143,10 +156,13 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,
 static inline unsigned long
 gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)
 {
+	union gpio_chip_reg rg;
+
 	if (WARN_ON(!chip->read_reg))
 		return 0;
 
-	return chip->read_reg(reg);
+	rg.mmio = reg;
+	return chip->read_reg(&rg);
 }
 
 /**
@@ -158,10 +174,13 @@ gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)
 static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,
 					  void __iomem *reg, unsigned long val)
 {
+	union gpio_chip_reg rg;
+
 	if (WARN_ON(!chip->write_reg))
 		return;
 
-	chip->write_reg(reg, val);
+	rg.mmio = reg;
+	chip->write_reg(&rg, val);
 }
 
 #define gpio_generic_chip_lock(gen_gc) \
-- 
2.53.0

[RFC PATCH v2 2/3] gpio: mmio: add port-mapped read/write callbacks

[Jose Javier Rodriguez Barbarin]

Implement PMIO read and write callbacks for 8-, 16- and 32-bit
register accesses using the corresponding port I/O helpers.

Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>
---
 drivers/gpio/gpio-mmio.c | 94 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c
index 39326ab7e494..d23c5d275e6b 100644
--- a/drivers/gpio/gpio-mmio.c
+++ b/drivers/gpio/gpio-mmio.c
@@ -124,6 +124,60 @@ static unsigned long gpio_mmio_read32be(union gpio_chip_reg *reg)
 	return ioread32be(reg->mmio);
 }
 
+#ifdef CONFIG_HAS_IOPORT
+
+static void gpio_port_write8(union gpio_chip_reg *reg, unsigned long data)
+{
+	outb(data, reg->port);
+}
+
+static unsigned long gpio_port_read8(union gpio_chip_reg *reg)
+{
+	return inb(reg->port);
+}
+
+static void gpio_port_write16(union gpio_chip_reg *reg, unsigned long data)
+{
+	outw(data, reg->port);
+}
+
+static unsigned long gpio_port_read16(union gpio_chip_reg *reg)
+{
+	return inw(reg->port);
+}
+
+static void gpio_port_write32(union gpio_chip_reg *reg, unsigned long data)
+{
+	outl(data, reg->port);
+}
+
+static unsigned long gpio_port_read32(union gpio_chip_reg *reg)
+{
+	return inl(reg->port);
+}
+
+static void gpio_port_write16be(union gpio_chip_reg *reg, unsigned long data)
+{
+	outw(swab16(data), reg->port);
+}
+
+static unsigned long gpio_port_read16be(union gpio_chip_reg *reg)
+{
+	return swab16(inw(reg->port));
+}
+
+static void gpio_port_write32be(union gpio_chip_reg *reg, unsigned long data)
+{
+	outl(swab32(data), reg->port);
+}
+
+static unsigned long gpio_port_read32be(union gpio_chip_reg *reg)
+{
+	return swab32(inl(reg->port));
+}
+
+#endif /* CONFIG_HAS_IOPORT */
+
 static inline bool gpio_chip_reg_is_set(union gpio_chip_reg *reg)
 {
 	return reg->port != 0;
@@ -462,6 +516,46 @@ static int gpio_mmio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
 	return gpio_mmio_dir_return(gc, gpio, true);
 }
 
+static int gpio_port_setup_accessors(struct device *dev,
+				     struct gpio_generic_chip *chip,
+				     bool byte_be)
+{
+#ifdef CONFIG_HAS_IOPORT
+	switch (chip->bits) {
+	case 8:
+		chip->read_reg	= gpio_port_read8;
+		chip->write_reg	= gpio_port_write8;
+		break;
+	case 16:
+		if (byte_be) {
+			chip->read_reg	= gpio_port_read16be;
+			chip->write_reg	= gpio_port_write16be;
+		} else {
+			chip->read_reg	= gpio_port_read16;
+			chip->write_reg	= gpio_port_write16;
+		}
+		break;
+	case 32:
+		if (byte_be) {
+			chip->read_reg	= gpio_port_read32be;
+			chip->write_reg	= gpio_port_write32be;
+		} else {
+			chip->read_reg	= gpio_port_read32;
+			chip->write_reg	= gpio_port_write32;
+		}
+		break;
+	default:
+		dev_err(dev, "unsupported data width %u bits\n", chip->bits);
+		return -EINVAL;
+	}
+
+	return 0;
+#else
+	dev_err(dev, "not supported because of missing I/O resource\n");
+	return -ENXIO;
+#endif /* CONFIG_HAS_IOPORT */
+}
+
 static int gpio_mmio_setup_accessors(struct device *dev,
 				     struct gpio_generic_chip *chip,
 				     bool byte_be)
-- 
2.53.0

[RFC PATCH v2 3/3] gpio: mmio: add port-mapped support for gpio_generic_chip

[Jose Javier Rodriguez Barbarin]

Add a new structure gpio_generic_chip_port_config for configuring
PMIO chips. A new function gpio_generic_chip_port_init() allows to
configure them.

Add an io_port field to struct gpio_generic_chip to distinguish PMIO
from MMIO chips during initialization and select the proper register
accessors.

Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>
---
 drivers/gpio/gpio-mmio.c     | 30 ++++++++++++++++++++++++--
 include/linux/gpio/generic.h | 41 ++++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c
index d23c5d275e6b..01e2afd8d6f1 100644
--- a/drivers/gpio/gpio-mmio.c
+++ b/drivers/gpio/gpio-mmio.c
@@ -740,8 +740,12 @@ static int gpio_generic_chip_init_common(struct gpio_generic_chip *chip,
 	if (ret)
 		return ret;
 
-	ret = gpio_mmio_setup_accessors(dev, chip,
-				flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
+	if (chip->io_port)
+		ret = gpio_port_setup_accessors(dev, chip,
+					flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
+	else
+		ret = gpio_mmio_setup_accessors(dev, chip,
+					flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER);
 	if (ret)
 		return ret;
 
@@ -801,11 +805,33 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,
 	chip->reg_clr.mmio = cfg->clr;
 	chip->reg_dir_in.mmio = cfg->dirin;
 	chip->reg_dir_out.mmio = cfg->dirout;
+	chip->io_port = true;
 
 	return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);
 }
 EXPORT_SYMBOL_GPL(gpio_generic_chip_init);
 
+/**
+ * gpio_generic_chip_port_init() - Initialize a generic GPIO chip for I/O port devices
+ * @chip: Generic GPIO chip to set up.
+ * @cfg: Generic GPIO chip configuration.
+ *
+ * Returns 0 on success, negative error number on failure.
+ */
+int gpio_generic_chip_port_init(struct gpio_generic_chip *chip,
+			   const struct gpio_generic_chip_port_config *cfg)
+{
+	chip->reg_dat.port = cfg->dat;
+	chip->reg_set.port = cfg->set;
+	chip->reg_clr.port = cfg->clr;
+	chip->reg_dir_in.port = cfg->dirin;
+	chip->reg_dir_out.port = cfg->dirout;
+	chip->io_port = true;
+
+	return gpio_generic_chip_init_common(chip, cfg->sz, cfg->flags, cfg->dev);
+}
+EXPORT_SYMBOL_GPL(gpio_generic_chip_port_init);
+
 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
 
 static void __iomem *gpio_mmio_map(struct platform_device *pdev,
diff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h
index 30f0d87422e9..93ce5f09c0d3 100644
--- a/include/linux/gpio/generic.h
+++ b/include/linux/gpio/generic.h
@@ -56,6 +56,43 @@ struct gpio_generic_chip_config {
 	unsigned long flags;
 };
 
+/**
+ * struct gpio_generic_chip_port_config - Generic GPIO chip configuration data for I/O port devices
+ * @dev: Parent device of the new GPIO chip (compulsory).
+ * @sz: Size (width) of the PMIO registers in bytes, typically 1, 2 or 4.
+ * @dat: PMIO address for the register to READ the value of the GPIO lines, it
+ *       is expected that a 1 in the corresponding bit in this register means
+ *       the line is asserted.
+ * @set: PMIO address for the register to SET the value of the GPIO lines, it
+ *       is expected that we write the line with 1 in this register to drive
+ *       the GPIO line high.
+ * @clr: PMIO address for the register to CLEAR the value of the GPIO lines,
+ *       it is expected that we write the line with 1 in this register to
+ *       drive the GPIO line low. It is allowed to leave this address as NULL,
+ *       in that case the SET register will be assumed to also clear the GPIO
+ *       lines, by actively writing the line with 0.
+ * @dirout: PMIO address for the register to set the line as OUTPUT. It is
+ *          assumed that setting a line to 1 in this register will turn that
+ *          line into an output line. Conversely, setting the line to 0 will
+ *          turn that line into an input.
+ * @dirin: PMIO address for the register to set this line as INPUT. It is
+ *         assumed that setting a line to 1 in this register will turn that
+ *         line into an input line. Conversely, setting the line to 0 will
+ *         turn that line into an output.
+ * @flags: Different flags that will affect the behaviour of the device, such
+ *         as endianness etc.
+ */
+struct gpio_generic_chip_port_config {
+	struct device *dev;
+	unsigned long sz;
+	unsigned long dat;
+	unsigned long set;
+	unsigned long clr;
+	unsigned long dirout;
+	unsigned long dirin;
+	unsigned long flags;
+};
+
 /**
  * union gpio_chip_reg - Generic GPIO chip register descriptor for MMIO or port-mapped I/O
  * @mmio: MMIO register address.
@@ -79,6 +116,7 @@ union gpio_chip_reg {
  *           representing line 0, bit 30 is line 1 ... bit 0 is line 31) this
  *           is set to true by the generic GPIO core. It is for internal
  *           housekeeping only.
+ * @io_port: indicates that the device is I/O port-mapped
  * @reg_dat: data (in) register for generic GPIO
  * @reg_set: output set register (out=high) for generic GPIO
  * @reg_clr: output clear register (out=low) for generic GPIO
@@ -100,6 +138,7 @@ struct gpio_generic_chip {
 	unsigned long (*read_reg)(union gpio_chip_reg *reg);
 	void (*write_reg)(union gpio_chip_reg *reg, unsigned long data);
 	bool be_bits;
+	bool io_port;
 	union gpio_chip_reg reg_dat;
 	union gpio_chip_reg reg_set;
 	union gpio_chip_reg reg_clr;
@@ -122,6 +161,8 @@ to_gpio_generic_chip(struct gpio_chip *gc)
 int gpio_generic_chip_init(struct gpio_generic_chip *chip,
 			   const struct gpio_generic_chip_config *cfg);
 
+int gpio_generic_chip_port_init(struct gpio_generic_chip *chip,
+				const struct gpio_generic_chip_port_config *cfg);
 /**
  * gpio_generic_chip_set() - Set the GPIO line value of the generic GPIO chip.
  * @chip: Generic GPIO chip to use.
-- 
2.53.0

Re: [RFC PATCH v2 1/3] gpio: mmio: convert accessors to generic register descriptors

[Linus Walleij]

On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:

> Convert the gpio-mmio accessors to use union gpio_chip_reg instead of
> the previous MMIO-only register type.
>
> This allows the same accessors to operate on both MMIO and PMIO
> registers and aligns gpio-mmio with the updated gpio_generic_chip API.
>
> Move the initialization code shared by MMIO and PMIO devices to a new
> function gpio_generic_chip_init_common(), leaving gpio_generic_chip_init()
> with the MMIO-specific initialization.
>
> Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>

This solution looks elegant to me:
Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

Re: [RFC PATCH v2 2/3] gpio: mmio: add port-mapped read/write callbacks

[Linus Walleij]

On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:

> Implement PMIO read and write callbacks for 8-, 16- and 32-bit
> register accesses using the corresponding port I/O helpers.
>
> Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

Re: [RFC PATCH v2 3/3] gpio: mmio: add port-mapped support for gpio_generic_chip

[Linus Walleij]

On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:

> Add a new structure gpio_generic_chip_port_config for configuring
> PMIO chips. A new function gpio_generic_chip_port_init() allows to
> configure them.
>
> Add an io_port field to struct gpio_generic_chip to distinguish PMIO
> from MMIO chips during initialization and select the proper register
> accessors.
>
> Signed-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>

Reviewed-by: Linus Walleij <linusw@kernel.org>

Yours,
Linus Walleij

Re: [RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Linus Walleij]

On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:

> This series is an RFC for adding port-mapped I/O (PMIO) support to
> gpio-mmio.
>
> This v2 comes with all suggestions done by Linux Walleij in the
> initial review [1].

That name! ;)

> For keeping compatibility with gpio_generic_chip, a new _config struct
> was added instead of extending gpio_generic_chip_config. Using such new
> _config struct, called gpio_generic_chip_port_config, requires a new API
> function gpio_generic_chip_port_init() to access to that new structure.
>
> Besides, structure gpio_chip_reg has been transformed to union. It reflects
> better that MMIO and PMIO chips will only use one of them, saving memory
> as well.
>
> I'm still sending this as RFC but I don't know if I should send this as a
> regular PATCH series.

I think we will usually only merge infrastructure if there is also a
consumer/user of it going in at the same time so these patches will
need to be prepended to a driver patch.

Yours,
Linus Walleij

Re: [RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Bartosz Golaszewski]

On Wed, Apr 22, 2026 at 6:44 PM Linus Walleij <linusw@kernel.org> wrote:
>
> On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
> <dev-josejavier.rodriguez@duagon.com> wrote:
>
> > This series is an RFC for adding port-mapped I/O (PMIO) support to
> > gpio-mmio.
> >
> > This v2 comes with all suggestions done by Linux Walleij in the
> > initial review [1].
>
> That name! ;)
>
> > For keeping compatibility with gpio_generic_chip, a new _config struct
> > was added instead of extending gpio_generic_chip_config. Using such new
> > _config struct, called gpio_generic_chip_port_config, requires a new API
> > function gpio_generic_chip_port_init() to access to that new structure.
> >
> > Besides, structure gpio_chip_reg has been transformed to union. It reflects
> > better that MMIO and PMIO chips will only use one of them, saving memory
> > as well.
> >
> > I'm still sending this as RFC but I don't know if I should send this as a
> > regular PATCH series.
>
> I think we will usually only merge infrastructure if there is also a
> consumer/user of it going in at the same time so these patches will
> need to be prepended to a driver patch.
>

Agreed. If the driver in question is not targetting drivers/gpio/, I
can provide an immutable branch with these patches.

Bart

Re: [RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Jose Javier Rodriguez Barbarin]

On Wed, Apr 22, 2026 at 06:44:37PM +0200, Linus Walleij wrote:
> On Mon, Apr 13, 2026 at 12:24 PM Jose Javier Rodriguez Barbarin
> <dev-josejavier.rodriguez@duagon.com> wrote:
>
> > This series is an RFC for adding port-mapped I/O (PMIO) support to
> > gpio-mmio.
> >
> > This v2 comes with all suggestions done by Linux Walleij in the
> > initial review [1].
>
> That name! ;)

Oh, I'm so sorry. :'(

>
> > For keeping compatibility with gpio_generic_chip, a new _config struct
> > was added instead of extending gpio_generic_chip_config. Using such new
> > _config struct, called gpio_generic_chip_port_config, requires a new API
> > function gpio_generic_chip_port_init() to access to that new structure.
> >
> > Besides, structure gpio_chip_reg has been transformed to union. It reflects
> > better that MMIO and PMIO chips will only use one of them, saving memory
> > as well.
> >
> > I'm still sending this as RFC but I don't know if I should send this as a
> > regular PATCH series.
>
> I think we will usually only merge infrastructure if there is also a
> consumer/user of it going in at the same time so these patches will
> need to be prepended to a driver patch.

Thank you so much. So, as far as I understand, my patches will be applied
once one or more drivers use those changes, isn't it?

All this started because I tried to provide I/O port support to gpio-menz127
however to apply those changes I have to add other changes on drivers/mcb
first. I'm currently working on it.

I'm aware there are still few I/O port-mapped I/O drivers so I would like
to continue with the TODO "task", trying to move those drivers to use this.

>
> Yours,
> Linus Walleij

Regards,

Javier R.

Re: [RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Bartosz Golaszewski]

On Thu, Apr 23, 2026 at 5:14 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:
>
> >
> > I think we will usually only merge infrastructure if there is also a
> > consumer/user of it going in at the same time so these patches will
> > need to be prepended to a driver patch.
>
> Thank you so much. So, as far as I understand, my patches will be applied
> once one or more drivers use those changes, isn't it?
>

More precisely: we can consider picking it up once you post a patch
that uses it proving that it's worth having it upstream.

> All this started because I tried to provide I/O port support to gpio-menz127
> however to apply those changes I have to add other changes on drivers/mcb
> first. I'm currently working on it.
>
> I'm aware there are still few I/O port-mapped I/O drivers so I would like
> to continue with the TODO "task", trying to move those drivers to use this.
>

Bart

Re: [RFC PATCH v2 0/3] gpio: add PMIO support to gpio-mmio

[Linus Walleij]

On Thu, Apr 23, 2026 at 5:14 PM Jose Javier Rodriguez Barbarin
<dev-josejavier.rodriguez@duagon.com> wrote:

> > I think we will usually only merge infrastructure if there is also a
> > consumer/user of it going in at the same time so these patches will
> > need to be prepended to a driver patch.
>
> Thank you so much. So, as far as I understand, my patches will be applied
> once one or more drivers use those changes, isn't it?

Yeah just put some driver patch last in the series so we see "OK it's
being used, looks good" and we (Bart) will merge it.

Yours,
Linus Walleij