Re: [PATCH] clk: qcom: gcc: Set FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON for PCIe pipe clocks

[Qiang Yu <qiang.yu@oss.qualcomm.com>]

On Thu, Jul 16, 2026 at 10:35:03AM +0530, Taniya Das wrote:
> 
> 
> On 7/15/2026 11:53 AM, Qiang Yu wrote:
> > Setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON for the PCIe PIPE
> > clocks so that the inbound data path works correctly.
> > 
> > Without this, the PCIe link can come up but the endpoint can not access
> > host memory, with the host sometimes seeing a completion timeout
> > reported by the EP, even though the host can still read the EP's config
> > space.
> > 
> > This issue is seen on QDU1000, Kaanapali, Glymur and Nord. Hence, apply
> > FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on these
> > platforms.
> > 
> 
> I do not see any such requirement in your code downstream, so trying to
> understand a why both the memory and peripheral needs to be set?
>
In downstream kernel, we set them for kaanapali. I met similar issue
when enabling PCIe3a x8 mode, after debugging, PCIe HW team recommends to
set them. But to be honest, I don't understand how this two bits affect.

> As I understand this was not concluded with design to understand the
> reasoning behind this change.
>
I started a mail thread to discuss it. Can you please help invlove gcc
design team to help us understand it? I'd be happy to have your team take
over posting the follow-up patch, if you're willing - this is really
your area of expertise. In this patch, I only added for nord kaanapli,
glymur and QDU1000, but other platforms may also require them.

- Qiang Yu