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From: Thomas Gleixner <tglx@linutronix.de>
To: Waiman Long <Waiman.Long@hpe.com>
Cc: Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org,
	Borislav Petkov <bp@suse.de>, Andy Lutomirski <luto@kernel.org>,
	Dave Hansen <dave.hansen@intel.com>,
	Prarit Bhargava <prarit@redhat.com>,
	Scott J Norton <scott.norton@hpe.com>,
	Douglas Hatch <doug.hatch@hpe.com>,
	Randy Wright <rwright@hpe.com>
Subject: Re: [RESEND PATCH v6] x86/hpet: Reduce HPET counter read contention
Date: Tue, 6 Sep 2016 17:50:14 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1609061749250.5647@nanos> (raw)
In-Reply-To: <1473175676-27713-1-git-send-email-Waiman.Long@hpe.com>

On Tue, 6 Sep 2016, Waiman Long wrote:
> 
> This is done by using a combination word with a sequence number and
> a bit lock. The CPU that gets the bit lock will be responsible for
> reading the HPET counter and update the sequence number. The others
> will monitor the change in sequence number and grab the HPET counter
> value accordingly. This change is only enabled on SMP configuration.

That hardly matches the implementation.
 
Thanks,

	tglx

  parent reply	other threads:[~2016-09-06 15:52 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-06 15:27 Waiman Long
2016-09-06 15:33 ` Prarit Bhargava
2016-09-06 15:45 ` Waiman Long
2016-09-06 15:50 ` Thomas Gleixner [this message]
2016-09-06 17:10   ` Waiman Long

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