From: Thomas Gleixner <tglx@linutronix.de>
To: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: vikas.shivappa@intel.com, linux-kernel@vger.kernel.org,
x86@kernel.org, hpa@zytor.com, mingo@kernel.org,
peterz@infradead.org, ravi.v.shankar@intel.com,
tony.luck@intel.com, fenghua.yu@intel.com, andi.kleen@intel.com
Subject: Re: [PATCH 5/5] x86/intel_rdt: hotcpu updates for RDT
Date: Wed, 1 Mar 2017 15:24:59 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.20.1703011511320.4005@nanos> (raw)
In-Reply-To: <1487360328-6768-6-git-send-email-vikas.shivappa@linux.intel.com>
On Fri, 17 Feb 2017, Vikas Shivappa wrote:
> For closid and rmid, change both the per cpu cache and PQR_MSR to be
> cleared only when offlining cpu at the respective handlers. The other
> places to clear them may not be required and is removed. This can be
> done at offlining so that the cache occupancy is not counted soon after
> the cpu goes down, rather than waiting to clear it during online cpu.
Yet another unstructured lump of blurb describing the WHAT and not the WHY.
> diff --git a/arch/x86/events/intel/cqm.c b/arch/x86/events/intel/cqm.c
> index 8c00dc0..681e32f 100644
> --- a/arch/x86/events/intel/cqm.c
> +++ b/arch/x86/events/intel/cqm.c
> @@ -1569,13 +1569,8 @@ static inline void cqm_pick_event_reader(int cpu)
>
> static int intel_cqm_cpu_starting(unsigned int cpu)
> {
> - struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
> struct cpuinfo_x86 *c = &cpu_data(cpu);
>
> - state->rmid = 0;
> - state->closid = 0;
> - state->rmid_usecnt = 0;
> -
> WARN_ON(c->x86_cache_max_rmid != cqm_max_rmid);
> WARN_ON(c->x86_cache_occ_scale != cqm_l3_scale);
>
> @@ -1585,12 +1580,17 @@ static int intel_cqm_cpu_starting(unsigned int cpu)
>
> static int intel_cqm_cpu_exit(unsigned int cpu)
> {
> + struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
Can be this_cpu_ptr() because the callback is guaranteed to run on the
outgoing CPU.
> int target;
>
> /* Is @cpu the current cqm reader for this package ? */
> if (!cpumask_test_and_clear_cpu(cpu, &cqm_cpumask))
> return 0;
So if the CPU is not the current cqm reader then the per cpu state of this
CPU is left stale. Great improvement.
> + state->rmid = 0;
> + state->rmid_usecnt = 0;
> + wrmsr(MSR_IA32_PQR_ASSOC, 0, state->closid);
What clears state->closid? And what guarantees that state->rmid is not
updated before the CPU has really gone away?
I doubt that this is correct, but if it is, then this lacks a big fat
comment explaining WHY.
Thanks,
tglx
next prev parent reply other threads:[~2017-03-01 15:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-17 19:38 [PATCH 0/5] x86/intel_rdt: Improvements/Fixes to RDT framework Vikas Shivappa
2017-02-17 19:38 ` [PATCH 1/5] x86/intel_rdt: Update control registers only when user really modifies it Vikas Shivappa
2017-03-01 13:31 ` Thomas Gleixner
2017-03-10 0:00 ` Shivappa Vikas
2017-02-17 19:38 ` [PATCH 2/5] x86/intel_rdt: Improvements to parsing schemata Vikas Shivappa
2017-03-01 14:03 ` Thomas Gleixner
2017-03-10 0:03 ` Shivappa Vikas
2017-03-10 10:53 ` Thomas Gleixner
2017-03-10 18:25 ` Shivappa Vikas
2017-03-10 18:58 ` Thomas Gleixner
2017-03-10 22:05 ` Luck, Tony
2017-03-11 7:47 ` Thomas Gleixner
2017-03-24 17:51 ` [PATCH] x86/intel_rdt: Implement "update" mode when writing schemata file Luck, Tony
2017-03-24 23:18 ` Fenghua Yu
2017-03-30 18:33 ` Shivappa Vikas
2017-03-31 8:24 ` Thomas Gleixner
2017-03-31 17:40 ` Shivappa Vikas
2017-03-31 17:49 ` Thomas Gleixner
2017-03-31 18:45 ` Shivappa Vikas
2017-02-17 19:38 ` [PATCH 3/5] x86/intel_rdt: Fail early on a resource with incorrect domains Vikas Shivappa
2017-03-01 14:05 ` Thomas Gleixner
2017-02-17 19:38 ` [PATCH 4/5] x86/intel_rdt: Reset the cbm MSR during rmdir Vikas Shivappa
2017-03-01 14:11 ` Thomas Gleixner
2017-03-10 1:45 ` Shivappa Vikas
2017-02-17 19:38 ` [PATCH 5/5] x86/intel_rdt: hotcpu updates for RDT Vikas Shivappa
2017-03-01 14:24 ` Thomas Gleixner [this message]
2017-03-30 19:03 ` Shivappa Vikas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.20.1703011511320.4005@nanos \
--to=tglx@linutronix.de \
--cc=andi.kleen@intel.com \
--cc=fenghua.yu@intel.com \
--cc=hpa@zytor.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=peterz@infradead.org \
--cc=ravi.v.shankar@intel.com \
--cc=tony.luck@intel.com \
--cc=vikas.shivappa@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®