From: Thomas Gleixner <tglx@linutronix.de>
To: Kan Liang <kan.liang@intel.com>
Cc: peterz@infradead.org, mingo@redhat.com,
linux-kernel@vger.kernel.org, bp@alien8.de, acme@kernel.org,
eranian@google.com, jolsa@kernel.org, ak@linux.intel.com
Subject: Re: [PATCH V7] perf/x86: add sysfs entry to freeze counter on SMI
Date: Tue, 23 May 2017 09:14:25 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.20.1705230913560.2740@nanos> (raw)
In-Reply-To: <1494600673-244667-1-git-send-email-kan.liang@intel.com>
On Fri, 12 May 2017, kan.liang@intel.com wrote:
> From: Kan Liang <Kan.liang@intel.com>
>
> Currently, the SMIs are visible to all performance counters. Because
> many users want to measure everything including SMIs. But in some
> cases, the SMI cycles should not be count. For example, to calculate
> the cost of SMI itself. So a knob is needed.
>
> When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance
> counters will be effected. There is no way to do per-counter freeze
> on SMI. So it should not use the per-event interface (e.g. ioctl or
> event attribute) to set FREEZE_WHILE_SMM bit.
>
> Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM
> bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages
> while in SMM.
> Value has to be 0 or 1. It will be applied to all processors.
> Also serialize the entire setting so we don't get multiple concurrent
> threads trying to update to different values.
>
> Signed-off-by: Kan Liang <Kan.liang@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
next prev parent reply other threads:[~2017-05-23 7:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-12 14:51 kan.liang
2017-05-19 12:42 ` Liang, Kan
2017-05-23 7:14 ` Thomas Gleixner [this message]
2017-05-23 8:40 ` [tip:perf/core] perf/x86: Add sysfs entry to freeze counters " tip-bot for Kan Liang
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