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From: Linus Torvalds <torvalds@linux-foundation.org>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Nick Piggin <npiggin@suse.de>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Andi Kleen <ak@suse.de>
Subject: Re: [patch] x86: improved memory barrier implementation
Date: Fri, 28 Sep 2007 09:15:06 -0700 (PDT)	[thread overview]
Message-ID: <alpine.LFD.0.999.0709280911100.3579@woody.linux-foundation.org> (raw)
In-Reply-To: <20070928170719.2f617a7a@the-village.bc.nu>



On Fri, 28 Sep 2007, Alan Cox wrote:
> 
> However 
> - You've not shown the patch has any performance gain

It would be nice to see this.

> - You've probably broken Pentium Pro

Probably not a big deal, but yeah, we should have that broken-ppro option.

> - and for modern processors its still not remotely clear your patch is
> correct because of NT stores.

This one I disagree with. The *old* code doesn't honor NT stores *either*. 

The fact is, if you use NT stores and then depend on ordering, it has 
nothing what-so-ever to do with spinlocks or smp_[rw]mb. You need to use 
the DMA barriers (ie the non-smp ones).

The non-temporal stores should be basically considered to be "IO", not any 
normal memory operation.

		Linus

  reply	other threads:[~2007-09-28 16:15 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2007-09-28 15:48 Nick Piggin
2007-09-28 16:07 ` Alan Cox
2007-09-28 16:15   ` Linus Torvalds [this message]
2007-09-29 13:17     ` Nick Piggin
2007-09-29 16:07       ` Linus Torvalds
2007-09-30 12:16         ` Nick Piggin
2007-09-28 16:54   ` Nick Piggin
2007-09-28 17:18     ` Alan Cox
2007-09-29 13:19       ` Nick Piggin
2007-09-30  1:43   ` Dave Jones

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