[PATCH v2 7/10] x86/tsc: enable APB timer based calibration

[PATCH v2 7/10] x86/tsc: enable APB timer based calibration

[Pan, Jacob jun]

>From e9264a1e5f8662d64f7d042544a03504b325bac9 Mon Sep 17 00:00:00 2001
From: Jacob Pan <jacob.jun.pan@intel.com>
Date: Wed, 15 Jul 2009 14:20:02 -0700
Subject: [PATCH] x86/tsc: enable APB timer based calibration

for platform that do not have PIT, we can use APB timer (if available)
to calibrate TSC by counting the two. APB timer frequency is known to
the system by SFI table provided by FW.

Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
---
 arch/x86/kernel/tsc.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 6e1a368..8b38a9d 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -18,6 +18,9 @@
 #include <asm/delay.h>
 #include <asm/hypervisor.h>
 
+#include <asm/platform_feature.h>
+#include <asm/apb_timer.h>
+
 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
 EXPORT_SYMBOL(cpu_khz);
 
@@ -394,6 +397,14 @@ unsigned long native_calibrate_tsc(void)
 		return hv_tsc_khz;
 	}
 
+	/* first check if apb timer exist and is usable */
+	if (platform_has(X86_PLATFORM_FEATURE_APBT)) {
+		local_irq_save(flags);
+		fast_calibrate = apbt_quick_calibrate();
+		local_irq_restore(flags);
+		if (fast_calibrate)
+			return fast_calibrate;
+	}
 	local_irq_save(flags);
 	fast_calibrate = quick_pit_calibrate();
 	local_irq_restore(flags);
-- 
1.5.6.5

Re: [PATCH v2 7/10] x86/tsc: enable APB timer based calibration

[Thomas Gleixner]

On Thu, 16 Jul 2009, Pan, Jacob jun wrote:

> >From e9264a1e5f8662d64f7d042544a03504b325bac9 Mon Sep 17 00:00:00 2001
> From: Jacob Pan <jacob.jun.pan@intel.com>
> Date: Wed, 15 Jul 2009 14:20:02 -0700
> Subject: [PATCH] x86/tsc: enable APB timer based calibration
> 
> for platform that do not have PIT, we can use APB timer (if available)
> to calibrate TSC by counting the two. APB timer frequency is known to
> the system by SFI table provided by FW.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
> ---
>  arch/x86/kernel/tsc.c |   11 +++++++++++
>  1 files changed, 11 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
> index 6e1a368..8b38a9d 100644
> --- a/arch/x86/kernel/tsc.c
> +++ b/arch/x86/kernel/tsc.c
> @@ -18,6 +18,9 @@
>  #include <asm/delay.h>
>  #include <asm/hypervisor.h>
>  
> +#include <asm/platform_feature.h>
> +#include <asm/apb_timer.h>
> +
>  unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
>  EXPORT_SYMBOL(cpu_khz);
>  
> @@ -394,6 +397,14 @@ unsigned long native_calibrate_tsc(void)
>  		return hv_tsc_khz;
>  	}
>  
> +	/* first check if apb timer exist and is usable */
> +	if (platform_has(X86_PLATFORM_FEATURE_APBT)) {
> +		local_irq_save(flags);
> +		fast_calibrate = apbt_quick_calibrate();
> +		local_irq_restore(flags);
> +		if (fast_calibrate)
> +			return fast_calibrate;

  And what is calibrating the TSC here. There is not PIT or comes that
  magically when the APBT thing fails ?

> +	}
>  	local_irq_save(flags);
>  	fast_calibrate = quick_pit_calibrate();
>  	local_irq_restore(flags);
> -- 
> 1.5.6.5
> 
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