Re: [PATCH v3 06/13] drm: renesas: rz-du: Add RZ/G3L (R9A08G046) DU support

[Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>]

On Thu, Aug 27, 2026 at 10:12:25AM +0200, Tommaso Merciai wrote:
> Hi Biju,
> Thanks, for your patch.
> 
> On Wed, Aug 26, 2026 at 06:48:40PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> > 
> > Add Display Unit support for the Renesas RZ/G3L SoC (R9A08G046). It is
> > similar to the one found on RZ/G2L, but has LVDS support.
> > 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v2->v3:
> >  * Set duty cycle handling in DU encoder
> >  * Added min/max frequencies for DPI.
> > v1->v2:
> >  * Dropped the macro RZG2L_DU_FEATURE_SMUX2_DSI_CLK and RZG2L_DU_MAX_LVDS.
> >  * Dropped the variable rcdu from struct rzg2l_du_encoder.
> >  * Dropped the variable lvds from struct rzg2l_du_device.
> > ---
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  | 24 ++++++++++++++++++-
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  |  3 ++-
> >  .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  | 24 +++++++++++++++++++
> >  3 files changed, 49 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > index 3d13f61d3c97..6c2dc86abc7d 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > @@ -55,6 +55,26 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> >  	.mode_clock_max = 83500,
> >  };
> >  
> > +static const struct rzg2l_du_device_info rzg2l_du_r9a08g046_info = {
> > +	.channels_mask = BIT(0),
> > +	.routes = {
> > +		[RZG2L_DU_OUTPUT_DSI0] = {
> > +			.possible_outputs = BIT(0),
> > +			.port = 0,
> > +		},
> > +		[RZG2L_DU_OUTPUT_DPAD0] = {
> > +			.possible_outputs = BIT(0),
> > +			.port = 1,
> > +		},
> > +		[RZG2L_DU_OUTPUT_LVDS0] = {
> > +			.possible_outputs = BIT(0),
> > +			.port = 2,
> > +		},
> > +	},
> > +	.mode_clock_min = 5440,
> > +	.mode_clock_max = 87000,
> 
> Pixel clock must be within the following range:
> 
> 	– Parallel = 5.4 to 87 MHz
> 
> rzg2l_du_encoder_mode_valid() is checking the DPAD0
> output mode clock then here we should set:
> 
> 	.mode_clock_min = 5400,

Apart for that the rest LGTM.

Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind regards,
Tommaso

> 
> Thanks, Tommaso
> 
> 
> > +};
> > +
> >  static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
> >  	.channels_mask = BIT(0),
> >  	.routes = {
> > @@ -81,6 +101,7 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = {
> >  static const struct of_device_id rzg2l_du_of_table[] = {
> >  	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
> >  	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
> > +	{ .compatible = "renesas,r9a08g046-du", .data = &rzg2l_du_r9a08g046_info },
> >  	{ .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },
> >  	{ .compatible = "renesas,r9a09g077-du", .data = &rzg2l_du_r9a09g077_info },
> >  	{ /* sentinel */ }
> > @@ -92,7 +113,8 @@ const char *rzg2l_du_output_name(enum rzg2l_du_output output)
> >  {
> >  	static const char * const names[] = {
> >  		[RZG2L_DU_OUTPUT_DSI0] = "DSI0",
> > -		[RZG2L_DU_OUTPUT_DPAD0] = "DPAD0"
> > +		[RZG2L_DU_OUTPUT_DPAD0] = "DPAD0",
> > +		[RZG2L_DU_OUTPUT_LVDS0] = "LVDS0"
> >  	};
> >  
> >  	if (output >= ARRAY_SIZE(names))
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > index baf076d69cda..e9626ef37cde 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > @@ -25,6 +25,7 @@ struct drm_property;
> >  enum rzg2l_du_output {
> >  	RZG2L_DU_OUTPUT_DSI0,
> >  	RZG2L_DU_OUTPUT_DPAD0,
> > +	RZG2L_DU_OUTPUT_LVDS0,
> >  	RZG2L_DU_OUTPUT_MAX,
> >  };
> >  
> > @@ -33,7 +34,7 @@ enum rzg2l_du_output {
> >   * @possible_outputs: bitmask of possible outputs
> >   * @port: device tree port number corresponding to this output route
> >   *
> > - * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data
> > + * The DU has 3 possible outputs (DPAD0, DSI0, LVDS0). Output routing data
> >   * specify the valid SoC outputs, which CRTC can drive the output, and the type
> >   * of in-SoC encoder for the output.
> >   */
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > index 3d0999e4fcfd..a1b48973aa8e 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > @@ -7,6 +7,7 @@
> >   * Based on rcar_du_encoder.c
> >   */
> >  
> > +#include <linux/clk.h>
> >  #include <linux/export.h>
> >  #include <linux/of.h>
> >  
> > @@ -15,6 +16,7 @@
> >  #include <drm/drm_bridge_connector.h>
> >  #include <drm/drm_panel.h>
> >  
> > +#include "rzg2l_du_crtc.h"
> >  #include "rzg2l_du_drv.h"
> >  #include "rzg2l_du_encoder.h"
> >  
> > @@ -64,8 +66,30 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
> >  	return MODE_OK;
> >  }
> >  
> > +static void rzg2l_du_encoder_atomic_mode_set(struct drm_encoder *encoder,
> > +					     struct drm_crtc_state *crtc_state,
> > +					     struct drm_connector_state *conn_state)
> > +{
> > +	struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> > +	struct rzg2l_du_crtc *rcrtc = to_rzg2l_crtc(crtc_state->crtc);
> > +	struct clk *clk_parent;
> > +
> > +	clk_parent = clk_get_parent(rcrtc->rzg2l_clocks.dclk);
> > +
> > +	/*
> > +	 * Request appropriate duty cycle
> > +	 * - LVDS path has DUTY H/L=4/3, 4/7 duty cycle.
> > +	 * - DSI/RGB path has symmetric 50% duty cycle.
> > +	 */
> > +	if (renc->output == RZG2L_DU_OUTPUT_LVDS0)
> > +		clk_set_duty_cycle(clk_parent, 4, 7);
> > +	else
> > +		clk_set_duty_cycle(clk_parent, 1, 2);
> > +}
> > +
> >  static const struct drm_encoder_helper_funcs rzg2l_du_encoder_helper_funcs = {
> >  	.mode_valid = rzg2l_du_encoder_mode_valid,
> > +	.atomic_mode_set = rzg2l_du_encoder_atomic_mode_set,
> >  };
> >  
> >  int rzg2l_du_encoder_init(struct rzg2l_du_device  *rcdu,
> > -- 
> > 2.43.0
> > 
>