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* [PATCH] PCI: tegra: Unwind partial PHY power-on failures
@ 2026-08-28  9:17 Pengpeng Hou
  2026-08-28 12:10 ` Thierry Reding
  0 siblings, 1 reply; 2+ messages in thread
From: Pengpeng Hou @ 2026-08-28  9:17 UTC (permalink / raw)
  To: Thierry Reding, Lorenzo Pieralisi
  Cc: Pengpeng Hou, Krzysztof Wilczyński, Manivannan Sadhasivam,
	Rob Herring, Bjorn Helgaas, Jonathan Hunter, linux-tegra,
	linux-pci, linux-kernel

The Tegra PCIe PHY setup has two nested acquisition loops.  Failure in a
per-port loop leaves earlier PHYs in that port powered, while failure in
the outer loop leaves all earlier ports powered.

Unwind the successfully powered PHYs in reverse order at both levels
before returning the original error.

The issue was identified via static analysis and manually reviewed.

Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs")

Assisted-by: LLM
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
 drivers/pci/controller/pci-tegra.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 59b56446c507..443fa33b7f0e 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -1002,6 +1002,8 @@ static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
 		err = phy_power_on(port->phys[i]);
 		if (err < 0) {
 			dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
+			while (i--)
+				phy_power_off(port->phys[i]);
 			return err;
 		}
 	}
@@ -1051,6 +1053,8 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
 			dev_err(dev,
 				"failed to power on PCIe port %u PHY: %d\n",
 				port->index, err);
+			list_for_each_entry_continue_reverse(port, &pcie->ports, list)
+				tegra_pcie_port_phy_power_off(port);
 			return err;
 		}
 	}
-- 
2.43.0


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] PCI: tegra: Unwind partial PHY power-on failures
  2026-08-28  9:17 [PATCH] PCI: tegra: Unwind partial PHY power-on failures Pengpeng Hou
@ 2026-08-28 12:10 ` Thierry Reding
  0 siblings, 0 replies; 2+ messages in thread
From: Thierry Reding @ 2026-08-28 12:10 UTC (permalink / raw)
  To: Pengpeng Hou
  Cc: Lorenzo Pieralisi, Krzysztof Wilczyński,
	Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
	Jonathan Hunter, linux-tegra, linux-pci, linux-kernel

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On Fri, Aug 28, 2026 at 05:17:47PM +0800, Pengpeng Hou wrote:
> The Tegra PCIe PHY setup has two nested acquisition loops.  Failure in a
> per-port loop leaves earlier PHYs in that port powered, while failure in
> the outer loop leaves all earlier ports powered.
> 
> Unwind the successfully powered PHYs in reverse order at both levels
> before returning the original error.
> 
> The issue was identified via static analysis and manually reviewed.
> 
> Fixes: 6fe7c187e026 ("PCI: tegra: Support per-lane PHYs")
> 
> Assisted-by: LLM
> Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
> ---
>  drivers/pci/controller/pci-tegra.c | 4 ++++
>  1 file changed, 4 insertions(+)

We technically could do something like this, but honestly I don't see
the point. If this ever happened, it'd mean that either the system is
improperly designed, badly configured in device tree or somehow broken.
In either case the unwind isn't really going to save you.

Thierry

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^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2026-08-28 12:10 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
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2026-08-28  9:17 [PATCH] PCI: tegra: Unwind partial PHY power-on failures Pengpeng Hou
2026-08-28 12:10 ` Thierry Reding

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