[PATCH 0/8] KVM: selftests: Add Zhaoxin CPU support

[PATCH 0/8] KVM: selftests: Add Zhaoxin CPU support

[Ewan Hai-oc]

Add Zhaoxin CPU detection to KVM's x86 selftests and enable tests whose
VMX paths are applicable to Zhaoxin CPUs.  Zhaoxin CPUs report either
"CentaurHauls" or "  Shanghai  " as vendor string and expose a
VMX-compatible virtualization interface.

Patch 1 adds the common vendor detection.
Patches 2-4 allow applicable TDP, invalid guest state, and hypercall
tests to run on Zhaoxin CPUs.
Patch 5 keeps feature_msrs_test running when KVM does not expose PDCM,
allowing the test to run on some Zhaoxin CPUs that do not support PDCM.
Patches 6-8 handle the KVM-defined IA32_UCODE_REV initial value, Zhaoxin
nested exception error codes, and optional APIC-access virtualization.

The series is based on kvm-x86-next-2026.07.28.

Tested on a system with a Zhaoxin CPU:
    - feature_msrs_test
    - fix_hypercall_test
    - nested_exceptions_test
    - vmx_apic_access_test
    - vmx_exception_with_invalid_guest_state
    - nx_huge_pages_test

Frank Zhu (8):
  KVM: selftests: Add Zhaoxin (ZX) CPU detection support
  KVM: selftests: nx_huge_pages_test: Add TDP detection for Zhaoxin CPUs
  KVM: selftests: vmx_exception_with_invalid_guest_state: Support
    Zhaoxin CPUs
  KVM: selftests: fix_hypercall_test: Add Zhaoxin CPU support
  KVM: selftests: Skip PERF_CAPABILITIES vCPU checks without PDCM
  KVM: selftests: feature_msrs_test: Extend MSR_IA32_UCODE_REV quirk to
    Zhaoxin
  KVM: selftests: nested_exceptions_test: Add Zhaoxin CPU support
  KVM: selftests: vmx_apic_access_test: Check APIC virtualization
    support

 .../testing/selftests/kvm/include/x86/processor.h |  7 +++++++
 tools/testing/selftests/kvm/include/x86/vmx.h     |  1 +
 tools/testing/selftests/kvm/lib/x86/processor.c   |  5 ++++-
 tools/testing/selftests/kvm/lib/x86/vmx.c         | 15 +++++++++++++++
 .../testing/selftests/kvm/x86/feature_msrs_test.c | 15 ++++++++++++++-
 .../selftests/kvm/x86/fix_hypercall_test.c        |  2 +-
 .../selftests/kvm/x86/nested_exceptions_test.c    |  4 +++-
 .../selftests/kvm/x86/vmx_apic_access_test.c      |  1 +
 .../x86/vmx_exception_with_invalid_guest_state.c  |  2 +-
 9 files changed, 47 insertions(+), 5 deletions(-)


base-commit: 3c7d7f908d574277a845423ec32250a8d8df44c8
-- 
2.34.1

[PATCH 1/8] KVM: selftests: Add Zhaoxin (ZX) CPU detection support

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

Add infrastructure to detect Zhaoxin CPUs in KVM selftests. Zhaoxin
CPUs use vendor strings "CentaurHauls" or "  Shanghai  " and implement
VMX-compatible virtualization technology.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/include/x86/processor.h | 7 +++++++
 tools/testing/selftests/kvm/lib/x86/processor.c     | 3 +++
 2 files changed, 10 insertions(+)

diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
index b161174ece45..9840b583877c 100644
--- a/tools/testing/selftests/kvm/include/x86/processor.h
+++ b/tools/testing/selftests/kvm/include/x86/processor.h
@@ -23,6 +23,7 @@ extern bool host_cpu_is_intel;
 extern bool host_cpu_is_amd;
 extern bool host_cpu_is_hygon;
 extern bool host_cpu_is_amd_compatible;
+extern bool host_cpu_is_zx;
 extern u64 guest_tsc_khz;
 
 #ifndef MAX_NR_CPUID_ENTRIES
@@ -744,6 +745,12 @@ static inline bool this_cpu_is_hygon(void)
 	return this_cpu_vendor_string_is("HygonGenuine");
 }
 
+static inline bool this_cpu_is_zx(void)
+{
+	return this_cpu_vendor_string_is("CentaurHauls") ||
+	       this_cpu_vendor_string_is("  Shanghai  ");
+}
+
 static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
 {
 	u32 gprs[4];
diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index ef56dcefe011..a8ea591ebe8e 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -26,6 +26,7 @@ bool host_cpu_is_amd;
 bool host_cpu_is_intel;
 bool host_cpu_is_hygon;
 bool host_cpu_is_amd_compatible;
+bool host_cpu_is_zx;
 bool is_forced_emulation_enabled;
 u64 guest_tsc_khz;
 
@@ -816,6 +817,7 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus)
 	sync_global_to_guest(vm, host_cpu_is_amd);
 	sync_global_to_guest(vm, host_cpu_is_hygon);
 	sync_global_to_guest(vm, host_cpu_is_amd_compatible);
+	sync_global_to_guest(vm, host_cpu_is_zx);
 	sync_global_to_guest(vm, is_forced_emulation_enabled);
 	sync_global_to_guest(vm, pmu_errata_mask);
 
@@ -1430,6 +1432,7 @@ void kvm_selftest_arch_init(void)
 	host_cpu_is_amd = this_cpu_is_amd();
 	host_cpu_is_hygon = this_cpu_is_hygon();
 	host_cpu_is_amd_compatible = host_cpu_is_amd || host_cpu_is_hygon;
+	host_cpu_is_zx = this_cpu_is_zx();
 	is_forced_emulation_enabled = kvm_is_forced_emulation_enabled();
 
 	kvm_init_pmu_errata();
-- 
2.34.1

[PATCH 2/8] KVM: selftests: nx_huge_pages_test: Add TDP detection for Zhaoxin CPUs

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

Update the kvm_is_tdp_enabled() function to include Zhaoxin CPUs
when checking for EPT (Extended Page Tables) support. This ensures
that ZX CPUs use the appropriate TDP (Two-Dimensional Paging)
parameter check, similar to Intel CPUs.

The change modifies the condition to check for both Intel and ZX
CPUs before querying the EPT parameter, maintaining compatibility
with existing Intel systems while extending support to ZX CPU
systems.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/lib/x86/processor.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index a8ea591ebe8e..4688cb2b0092 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -156,7 +156,7 @@ static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, u8 indent)
 
 bool kvm_is_tdp_enabled(void)
 {
-	if (host_cpu_is_intel)
+	if (host_cpu_is_intel || host_cpu_is_zx)
 		return get_kvm_intel_param_bool("ept");
 	else
 		return get_kvm_amd_param_bool("npt");
-- 
2.34.1

[PATCH 3/8] KVM: selftests: vmx_exception_with_invalid_guest_state: Support Zhaoxin CPUs

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

The vmx_exception_with_invalid_guest_state test currently requires an
Intel CPU. However, Zhaoxin CPUs also support VMX and the relevant
invalid guest state handling under KVM.

Update the test requirement to allow execution on Zhaoxin platforms in
addition to Intel, enabling broader coverage of VMX-related error paths.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 .../selftests/kvm/x86/vmx_exception_with_invalid_guest_state.c  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/vmx_exception_with_invalid_guest_state.c b/tools/testing/selftests/kvm/x86/vmx_exception_with_invalid_guest_state.c
index 2cae86d9d5e2..e95dc4cd8adb 100644
--- a/tools/testing/selftests/kvm/x86/vmx_exception_with_invalid_guest_state.c
+++ b/tools/testing/selftests/kvm/x86/vmx_exception_with_invalid_guest_state.c
@@ -109,7 +109,7 @@ int main(int argc, char *argv[])
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 
-	TEST_REQUIRE(host_cpu_is_intel);
+	TEST_REQUIRE(host_cpu_is_intel || host_cpu_is_zx);
 	TEST_REQUIRE(!kvm_is_unrestricted_guest_enabled());
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
-- 
2.34.1

[PATCH 4/8] KVM: selftests: fix_hypercall_test: Add Zhaoxin CPU support

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

Zhaoxin CPUs offer a VMX-compatible interface with the same VMCALL
instruction as Intel CPUs for hypercalls. Add host_cpu_is_zx to the
Intel branch to allow the test to run correctly on Zhaoxin hardware.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/x86/fix_hypercall_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
index 753a0e730ea8..0fb75ad1715f 100644
--- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
+++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
@@ -49,7 +49,7 @@ static void guest_main(void)
 	const u8 *other_hypercall_insn;
 	u64 ret;
 
-	if (host_cpu_is_intel) {
+	if (host_cpu_is_intel || host_cpu_is_zx) {
 		native_hypercall_insn = vmx_vmcall;
 		other_hypercall_insn  = svm_vmmcall;
 	} else if (host_cpu_is_amd_compatible) {
-- 
2.34.1

[PATCH 5/8] KVM: selftests: Skip PERF_CAPABILITIES vCPU checks without PDCM

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

KVM allows userspace to query MSR_IA32_PERF_CAPABILITIES through
KVM_GET_MSRS even when PDCM is not exposed in KVM_GET_SUPPORTED_CPUID.
However, vCPU accesses to the MSR fail without PDCM.

Keep the feature MSR query, but skip its checks when KVM does not
expose PDCM, allowing feature_msrs_test to continue checking the
remaining feature MSRs.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/x86/feature_msrs_test.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/tools/testing/selftests/kvm/x86/feature_msrs_test.c b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
index 158550701771..9602e29bf9cc 100644
--- a/tools/testing/selftests/kvm/x86/feature_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
@@ -54,6 +54,19 @@ static void test_feature_msr(u32 msr)
 	if (is_kvm_controlled_msr(msr))
 		return;
 
+	/*
+	 * KVM allows userspace to query MSR_IA32_PERF_CAPABILITIES as a
+	 * feature MSR even if KVM doesn't expose PDCM, but vCPU accesses to
+	 * the MSR will fail in that case. Skip the vCPU checks so that the
+	 * remaining feature MSRs can be tested.
+	 */
+	if (msr == MSR_IA32_PERF_CAPABILITIES &&
+	    !kvm_cpu_has(X86_FEATURE_PDCM)) {
+		printf("KVM does not expose PDCM, skipping vCPU checks for "
+		       "MSR_IA32_PERF_CAPABILITIES (0x%x).\n", msr);
+		return;
+	}
+
 	/*
 	 * More goofy behavior.  KVM reports the host CPU's actual revision ID,
 	 * but initializes the vCPU's revision ID to an arbitrary value.
-- 
2.34.1

[PATCH 6/8] KVM: selftests: feature_msrs_test: Extend MSR_IA32_UCODE_REV quirk to Zhaoxin

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

Zhaoxin CPUs use KVM's VMX backend and therefore observe the same
KVM-defined initial value as Intel vCPUs. Update feature_msrs_test to
expect 0x100000000ULL for Zhaoxin vCPUs.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/x86/feature_msrs_test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/feature_msrs_test.c b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
index 9602e29bf9cc..c24fa5275a99 100644
--- a/tools/testing/selftests/kvm/x86/feature_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
@@ -72,7 +72,7 @@ static void test_feature_msr(u32 msr)
 	 * but initializes the vCPU's revision ID to an arbitrary value.
 	 */
 	if (msr == MSR_IA32_UCODE_REV)
-		reset_value = host_cpu_is_intel ? 0x100000000ULL : 0x01000065;
+		reset_value = (host_cpu_is_intel || host_cpu_is_zx) ? 0x100000000ULL : 0x01000065;
 
 	/*
 	 * For quirked MSRs, KVM's ABI is to initialize the vCPU's value to the
-- 
2.34.1

[PATCH 7/8] KVM: selftests: nested_exceptions_test: Add Zhaoxin CPU support

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

In the test, the ERROR_CODE_EXT_FLAG bit should not be set in the #GP
error code on Zhaoxin CPUs. Add GP_ERROR_CODE_ZX and use it when
running on Zhaoxin hardware.

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/x86/nested_exceptions_test.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
index aeec3121c8e8..bacbbdc5dc69 100644
--- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
@@ -38,6 +38,7 @@
  */
 #define GP_ERROR_CODE_AMD ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG)
 #define GP_ERROR_CODE_INTEL ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG | ERROR_CODE_EXT_FLAG)
+#define GP_ERROR_CODE_ZX ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG)
 
 /*
  * Intel and AMD both shove '0' into the error code on #DF, regardless of what
@@ -139,7 +140,8 @@ static void l1_vmx_code(struct vmx_pages *vmx)
 	 */
 	GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_GP_DF), 0);
 	vmx_run_l2(l2_ss_pending_test, SS_VECTOR, (u16)SS_ERROR_CODE);
-	vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR, GP_ERROR_CODE_INTEL);
+	vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR,
+		   host_cpu_is_zx ? GP_ERROR_CODE_ZX : GP_ERROR_CODE_INTEL);
 
 	GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_DF), 0);
 	vmx_run_l2(l2_ss_injected_df_test, DF_VECTOR, DF_ERROR_CODE);
-- 
2.34.1

[PATCH 8/8] KVM: selftests: vmx_apic_access_test: Check APIC virtualization support

[Ewan Hai-oc]

From: Frank Zhu <frankzhu@zhaoxin.com>

Not all CPUs that support VMX necessarily support the "virtualize APIC
accesses" secondary processor-based VM-execution control. For example,
some Zhaoxin CPUs lack this feature. Add a capability check before
running the test to properly skip on unsupported hardware instead of
failing.

Add kvm_cpu_has_vmx_apic_access_virt() helper to vmx.c, following the
same pattern as kvm_cpu_has_ept().

Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
---
 tools/testing/selftests/kvm/include/x86/vmx.h     |  1 +
 tools/testing/selftests/kvm/lib/x86/vmx.c         | 15 +++++++++++++++
 .../selftests/kvm/x86/vmx_apic_access_test.c      |  1 +
 3 files changed, 17 insertions(+)

diff --git a/tools/testing/selftests/kvm/include/x86/vmx.h b/tools/testing/selftests/kvm/include/x86/vmx.h
index 4bcfd60e3aec..d9e3bbd56040 100644
--- a/tools/testing/selftests/kvm/include/x86/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86/vmx.h
@@ -560,6 +560,7 @@ bool load_vmcs(struct vmx_pages *vmx);
 bool ept_1g_pages_supported(void);
 
 bool kvm_cpu_has_ept(void);
+bool kvm_cpu_has_vmx_apic_access_virt(void);
 void vm_enable_ept(struct kvm_vm *vm);
 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm);
 
diff --git a/tools/testing/selftests/kvm/lib/x86/vmx.c b/tools/testing/selftests/kvm/lib/x86/vmx.c
index cd09c9de4485..d634a0f00166 100644
--- a/tools/testing/selftests/kvm/lib/x86/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86/vmx.c
@@ -390,6 +390,21 @@ bool kvm_cpu_has_ept(void)
 	return ctrl & SECONDARY_EXEC_ENABLE_EPT;
 }
 
+bool kvm_cpu_has_vmx_apic_access_virt(void)
+{
+	u64 ctrl;
+
+	if (!kvm_cpu_has(X86_FEATURE_VMX))
+		return false;
+
+	ctrl = kvm_get_feature_msr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) >> 32;
+	if (!(ctrl & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
+		return false;
+
+	ctrl = kvm_get_feature_msr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32;
+	return ctrl & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
+}
+
 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm)
 {
 	vmx->apic_access = (void *)vm_alloc_page(vm);
diff --git a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
index 463f73aa9159..a1b6da4c0740 100644
--- a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
@@ -78,6 +78,7 @@ int main(int argc, char *argv[])
 	struct kvm_vm *vm;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX));
+	TEST_REQUIRE(kvm_cpu_has_vmx_apic_access_virt());
 
 	vm = vm_create_with_one_vcpu(&vcpu, l1_guest_code);
 
-- 
2.34.1

Re: [PATCH 1/8] KVM: selftests: Add Zhaoxin (ZX) CPU detection support

[Sean Christopherson]

On Thu, Jul 30, 2026, Ewan Hai-oc wrote:
> From: Frank Zhu <frankzhu@zhaoxin.com>
> 
> Add infrastructure to detect Zhaoxin CPUs in KVM selftests. Zhaoxin
> CPUs use vendor strings "CentaurHauls" or "  Shanghai  " and implement
> VMX-compatible virtualization technology.
> 
> Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  tools/testing/selftests/kvm/include/x86/processor.h | 7 +++++++
>  tools/testing/selftests/kvm/lib/x86/processor.c     | 3 +++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
> index b161174ece45..9840b583877c 100644
> --- a/tools/testing/selftests/kvm/include/x86/processor.h
> +++ b/tools/testing/selftests/kvm/include/x86/processor.h
> @@ -23,6 +23,7 @@ extern bool host_cpu_is_intel;
>  extern bool host_cpu_is_amd;
>  extern bool host_cpu_is_hygon;
>  extern bool host_cpu_is_amd_compatible;
> +extern bool host_cpu_is_zx;

Please spell out "zhaoxin", "zx" isn't intuitive for most of us (I keep thinking
it's a compression feature).

And do the same thing we did in commit 53b2869231d3 ("KVM: selftests: Add a flag
to identify AMD compatible test cases"), and add host_cpu_is_intel_compatible.
That should cut down on the number of checks on is_zhaoxin, and should help avoid
issues like the ones Sashiko pointed out.

Re: [PATCH 7/8] KVM: selftests: nested_exceptions_test: Add Zhaoxin CPU support

[Sean Christopherson]

On Thu, Jul 30, 2026, Ewan Hai-oc wrote:
> From: Frank Zhu <frankzhu@zhaoxin.com>
> 
> In the test, the ERROR_CODE_EXT_FLAG bit should not be set in the #GP
> error code on Zhaoxin CPUs.

Why not?

> Add GP_ERROR_CODE_ZX and use it when > running on Zhaoxin hardware.
> 
> Signed-off-by: Frank Zhu <frankzhu@zhaoxin.com>
> Signed-off-by: Ewan Hai <ewanhai-oc@zhaoxin.com>
> ---
>  tools/testing/selftests/kvm/x86/nested_exceptions_test.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
> index aeec3121c8e8..bacbbdc5dc69 100644
> --- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
> +++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
> @@ -38,6 +38,7 @@
>   */
>  #define GP_ERROR_CODE_AMD ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG)
>  #define GP_ERROR_CODE_INTEL ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG | ERROR_CODE_EXT_FLAG)
> +#define GP_ERROR_CODE_ZX ((SS_VECTOR * 8) | ERROR_CODE_IDT_FLAG)
>  
>  /*
>   * Intel and AMD both shove '0' into the error code on #DF, regardless of what
> @@ -139,7 +140,8 @@ static void l1_vmx_code(struct vmx_pages *vmx)
>  	 */
>  	GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_GP_DF), 0);
>  	vmx_run_l2(l2_ss_pending_test, SS_VECTOR, (u16)SS_ERROR_CODE);
> -	vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR, GP_ERROR_CODE_INTEL);
> +	vmx_run_l2(l2_ss_injected_gp_test, GP_VECTOR,
> +		   host_cpu_is_zx ? GP_ERROR_CODE_ZX : GP_ERROR_CODE_INTEL);
>  
>  	GUEST_ASSERT_EQ(vmwrite(EXCEPTION_BITMAP, INTERCEPT_SS_DF), 0);
>  	vmx_run_l2(l2_ss_injected_df_test, DF_VECTOR, DF_ERROR_CODE);
> -- 
> 2.34.1
> 
>