* [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path
@ 2026-08-13 10:54 Chaithanya Lagisetty
2026-08-13 16:37 ` Frank Li
0 siblings, 1 reply; 6+ messages in thread
From: Chaithanya Lagisetty @ 2026-08-13 10:54 UTC (permalink / raw)
To: Eugeniy Paltsev, Vinod Koul
Cc: Frank Li, Chaithanya Lagisetty, dmaengine, linux-kernel
axi_dma_resume() enables cfgr_clk and then core_clk. If enabling
core_clk fails, the function returns the error without disabling
cfgr_clk, which was already enabled, leaving the clock refcount
unbalanced.
Disable cfgr_clk on the core_clk enable failure path.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Signed-off-by: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index bcefaff03b5c..9db8993e0bc6 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1335,8 +1335,10 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
return ret;
ret = clk_prepare_enable(chip->core_clk);
- if (ret < 0)
+ if (ret < 0) {
+ clk_disable_unprepare(chip->cfgr_clk);
return ret;
+ }
axi_dma_enable(chip);
axi_dma_irq_enable(chip);
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path
2026-08-13 10:54 [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path Chaithanya Lagisetty
@ 2026-08-13 16:37 ` Frank Li
2026-08-16 5:48 ` [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API Chaithanya Lagisetty
0 siblings, 1 reply; 6+ messages in thread
From: Frank Li @ 2026-08-13 16:37 UTC (permalink / raw)
To: Chaithanya Lagisetty
Cc: Eugeniy Paltsev, Vinod Koul, Frank Li, dmaengine, linux-kernel
On Thu, Aug 13, 2026 at 10:54:32AM +0000, Chaithanya Lagisetty wrote:
> [You don't often get email from nagachaithanya9911@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> axi_dma_resume() enables cfgr_clk and then core_clk. If enabling
> core_clk fails, the function returns the error without disabling
> cfgr_clk, which was already enabled, leaving the clock refcount
> unbalanced.
>
> Disable cfgr_clk on the core_clk enable failure path.
>
> Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
> Signed-off-by: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
> ---
> drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index bcefaff03b5c..9db8993e0bc6 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1335,8 +1335,10 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
> return ret;
>
> ret = clk_prepare_enable(chip->core_clk);
> - if (ret < 0)
> + if (ret < 0) {
> + clk_disable_unprepare(chip->cfgr_clk);
> return ret;
> + }
convert driver by use clk bulk API.
Frank
>
> axi_dma_enable(chip);
> axi_dma_irq_enable(chip);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API
2026-08-13 16:37 ` Frank Li
@ 2026-08-16 5:48 ` Chaithanya Lagisetty
2026-08-19 19:22 ` Frank Li
2026-09-03 17:05 ` Vinod Koul
0 siblings, 2 replies; 6+ messages in thread
From: Chaithanya Lagisetty @ 2026-08-16 5:48 UTC (permalink / raw)
To: vkoul
Cc: Frank.Li, Frank.li, Eugeniy.Paltsev, dmaengine, linux-kernel,
Chaithanya Lagisetty
The driver managed its two mandatory clocks (core-clk and cfgr-clk)
individually. This was error prone: axi_dma_resume() enabled cfgr_clk
and then core_clk, and if enabling core_clk failed it returned the
error without disabling cfgr_clk, leaving the clock refcount
unbalanced.
Convert the driver to the clk_bulk API. The two clocks are always
acquired, enabled and disabled together, so a clk_bulk_data array
expresses this naturally and shrinks the get/enable/disable paths.
clk_bulk_prepare_enable() also unwinds any clock it already enabled
when a later one fails, which fixes the resume imbalance.
Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
Signed-off-by: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
---
Changes since v1:
- Convert the driver to the clk_bulk API instead of manually disabling
cfgr_clk on the error path, as suggested by Frank Li.
- v1: https://lore.kernel.org/all/20260813105432.2577322-1-nagachaithanya9911@gmail.com/
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 28 ++++++++-----------
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +-
2 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index bcefaff03b5c..254167a558ff 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip)
axi_dma_irq_disable(chip);
axi_dma_disable(chip);
- clk_disable_unprepare(chip->core_clk);
- clk_disable_unprepare(chip->cfgr_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks);
return 0;
}
@@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
{
int ret;
- ret = clk_prepare_enable(chip->cfgr_clk);
- if (ret < 0)
- return ret;
-
- ret = clk_prepare_enable(chip->core_clk);
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
if (ret < 0)
return ret;
@@ -1524,13 +1519,11 @@ static int dw_probe(struct platform_device *pdev)
chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
- chip->core_clk = devm_clk_get(chip->dev, "core-clk");
- if (IS_ERR(chip->core_clk))
- return PTR_ERR(chip->core_clk);
-
- chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
- if (IS_ERR(chip->cfgr_clk))
- return PTR_ERR(chip->cfgr_clk);
+ chip->clks[0].id = "core-clk";
+ chip->clks[1].id = "cfgr-clk";
+ ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
+ if (ret)
+ return dev_err_probe(chip->dev, ret, "failed to get clocks\n");
ret = parse_device_properties(chip);
if (ret)
@@ -1640,10 +1633,13 @@ static void dw_remove(struct platform_device *pdev)
struct dw_axi_dma *dw = chip->dw;
struct axi_dma_chan *chan, *_chan;
u32 i;
+ int ret;
/* Enable clk before accessing to registers */
- clk_prepare_enable(chip->cfgr_clk);
- clk_prepare_enable(chip->core_clk);
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
+ if (ret)
+ dev_warn(chip->dev, "failed to enable clocks before remove: %d\n",
+ ret);
axi_dma_irq_disable(chip);
for (i = 0; i < dw->hdata->nr_channels; i++) {
axi_chan_disable(&chip->dw->chan[i]);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 67cc199e24d1..039316c42f05 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -69,8 +69,7 @@ struct axi_dma_chip {
int irq[DMAC_MAX_CHANNELS];
void __iomem *regs;
void __iomem *apb_regs;
- struct clk *core_clk;
- struct clk *cfgr_clk;
+ struct clk_bulk_data clks[2];
struct dw_axi_dma *dw;
};
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API
2026-08-16 5:48 ` [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API Chaithanya Lagisetty
@ 2026-08-19 19:22 ` Frank Li
[not found] ` <CALFZYQUrxNp3W2WvL0oWWEKUFxKnLyfbYyOzE3aNBWWG-pf0kQ@mail.gmail.com>
2026-09-03 17:05 ` Vinod Koul
1 sibling, 1 reply; 6+ messages in thread
From: Frank Li @ 2026-08-19 19:22 UTC (permalink / raw)
To: Chaithanya Lagisetty
Cc: vkoul, Frank.Li, Eugeniy.Paltsev, dmaengine, linux-kernel
On Sun, Aug 16, 2026 at 05:48:58AM +0000, Chaithanya Lagisetty wrote:
> The driver managed its two mandatory clocks (core-clk and cfgr-clk)
> individually. This was error prone: axi_dma_resume() enabled cfgr_clk
> and then core_clk, and if enabling core_clk failed it returned the
> error without disabling cfgr_clk, leaving the clock refcount
> unbalanced.
>
> Convert the driver to the clk_bulk API. The two clocks are always
> acquired, enabled and disabled together, so a clk_bulk_data array
> expresses this naturally and shrinks the get/enable/disable paths.
> clk_bulk_prepare_enable() also unwinds any clock it already enabled
> when a later one fails, which fixes the resume imbalance.
>
> Fixes: 1fe20f1b8454 ("dmaengine: Introduce DW AXI DMAC driver")
> Signed-off-by: Chaithanya Lagisetty <nagachaithanya9911@gmail.com>
> ---
Again, don't post new patch to old patch's thread.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Changes since v1:
> - Convert the driver to the clk_bulk API instead of manually disabling
> cfgr_clk on the error path, as suggested by Frank Li.
> - v1: https://lore.kernel.org/all/20260813105432.2577322-1-nagachaithanya9911@gmail.com/
>
> .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 28 ++++++++-----------
> drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 3 +-
> 2 files changed, 13 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> index bcefaff03b5c..254167a558ff 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
> @@ -1320,8 +1320,7 @@ static int axi_dma_suspend(struct axi_dma_chip *chip)
> axi_dma_irq_disable(chip);
> axi_dma_disable(chip);
>
> - clk_disable_unprepare(chip->core_clk);
> - clk_disable_unprepare(chip->cfgr_clk);
> + clk_bulk_disable_unprepare(ARRAY_SIZE(chip->clks), chip->clks);
>
> return 0;
> }
> @@ -1330,11 +1329,7 @@ static int axi_dma_resume(struct axi_dma_chip *chip)
> {
> int ret;
>
> - ret = clk_prepare_enable(chip->cfgr_clk);
> - if (ret < 0)
> - return ret;
> -
> - ret = clk_prepare_enable(chip->core_clk);
> + ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
> if (ret < 0)
> return ret;
>
> @@ -1524,13 +1519,11 @@ static int dw_probe(struct platform_device *pdev)
>
> chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2);
>
> - chip->core_clk = devm_clk_get(chip->dev, "core-clk");
> - if (IS_ERR(chip->core_clk))
> - return PTR_ERR(chip->core_clk);
> -
> - chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk");
> - if (IS_ERR(chip->cfgr_clk))
> - return PTR_ERR(chip->cfgr_clk);
> + chip->clks[0].id = "core-clk";
> + chip->clks[1].id = "cfgr-clk";
> + ret = devm_clk_bulk_get(chip->dev, ARRAY_SIZE(chip->clks), chip->clks);
> + if (ret)
> + return dev_err_probe(chip->dev, ret, "failed to get clocks\n");
>
> ret = parse_device_properties(chip);
> if (ret)
> @@ -1640,10 +1633,13 @@ static void dw_remove(struct platform_device *pdev)
> struct dw_axi_dma *dw = chip->dw;
> struct axi_dma_chan *chan, *_chan;
> u32 i;
> + int ret;
>
> /* Enable clk before accessing to registers */
> - clk_prepare_enable(chip->cfgr_clk);
> - clk_prepare_enable(chip->core_clk);
> + ret = clk_bulk_prepare_enable(ARRAY_SIZE(chip->clks), chip->clks);
> + if (ret)
> + dev_warn(chip->dev, "failed to enable clocks before remove: %d\n",
> + ret);
> axi_dma_irq_disable(chip);
> for (i = 0; i < dw->hdata->nr_channels; i++) {
> axi_chan_disable(&chip->dw->chan[i]);
> diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> index 67cc199e24d1..039316c42f05 100644
> --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
> @@ -69,8 +69,7 @@ struct axi_dma_chip {
> int irq[DMAC_MAX_CHANNELS];
> void __iomem *regs;
> void __iomem *apb_regs;
> - struct clk *core_clk;
> - struct clk *cfgr_clk;
> + struct clk_bulk_data clks[2];
> struct dw_axi_dma *dw;
> };
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API
[not found] ` <CALFZYQUrxNp3W2WvL0oWWEKUFxKnLyfbYyOzE3aNBWWG-pf0kQ@mail.gmail.com>
@ 2026-09-03 16:08 ` Vinod Koul
0 siblings, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2026-09-03 16:08 UTC (permalink / raw)
To: naga chaithanya
Cc: Frank Li, Frank Li, Eugeniy Paltsev, dmaengine, linux-kernel
On 20-08-26, 08:32, naga chaithanya wrote:
> Hi Frank,
>
> Thanks for the review. I apologize for the threading error and will ensure
> future versions are sent as new threads.
and DO_NOT top post!
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API
2026-08-16 5:48 ` [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API Chaithanya Lagisetty
2026-08-19 19:22 ` Frank Li
@ 2026-09-03 17:05 ` Vinod Koul
1 sibling, 0 replies; 6+ messages in thread
From: Vinod Koul @ 2026-09-03 17:05 UTC (permalink / raw)
To: Chaithanya Lagisetty
Cc: Frank.Li, Frank.li, Eugeniy.Paltsev, dmaengine, linux-kernel
On Sun, 16 Aug 2026 05:48:58 +0000, Chaithanya Lagisetty wrote:
> The driver managed its two mandatory clocks (core-clk and cfgr-clk)
> individually. This was error prone: axi_dma_resume() enabled cfgr_clk
> and then core_clk, and if enabling core_clk failed it returned the
> error without disabling cfgr_clk, leaving the clock refcount
> unbalanced.
>
> Convert the driver to the clk_bulk API. The two clocks are always
> acquired, enabled and disabled together, so a clk_bulk_data array
> expresses this naturally and shrinks the get/enable/disable paths.
> clk_bulk_prepare_enable() also unwinds any clock it already enabled
> when a later one fails, which fixes the resume imbalance.
>
> [...]
Applied, thanks!
[1/1] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API
commit: 110126f425c34a2b189e10e74eec7644e1b47827
Best regards,
--
~Vinod
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-09-03 17:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-08-13 10:54 [PATCH] dmaengine: dw-axi-dmac: fix clock imbalance in resume error path Chaithanya Lagisetty
2026-08-13 16:37 ` Frank Li
2026-08-16 5:48 ` [PATCH v2] dmaengine: dw-axi-dmac: convert clock handling to clk_bulk API Chaithanya Lagisetty
2026-08-19 19:22 ` Frank Li
[not found] ` <CALFZYQUrxNp3W2WvL0oWWEKUFxKnLyfbYyOzE3aNBWWG-pf0kQ@mail.gmail.com>
2026-09-03 16:08 ` Vinod Koul
2026-09-03 17:05 ` Vinod Koul
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