Re: [PATCH v5 04/26] perf annotate-arm64: Handle load and store instructions

[Namhyung Kim <namhyung@kernel.org>]

On Tue, Sep 08, 2026 at 01:05:07PM +0000, Tengda Wu wrote:
> Add ldst_ops to handle load and store instructions in order to parse
> the data types and offsets associated with PMU events for memory access
> instructions. There are many variants of load and store instructions in
> arm64, making it difficult to match all of these instruction names
> completely. Therefore, only the instruction prefixes are matched. The
> prefix 'ld|st' covers most of the memory access instructions, 'cas|swp'
> matches atomic instructions, and 'prf' matches memory prefetch
> instructions.
> 
> Signed-off-by: Li Huafei <lihuafei1@huawei.com>
> Signed-off-by: Tengda Wu <wutengda@huaweicloud.com>

Reviewed-by: Namhyung Kim <namhyung@kernel.org>

Thanks,
Namhyung

> ---
>  .../perf/util/annotate-arch/annotate-arm64.c  | 140 ++++++++++++++++++
>  1 file changed, 140 insertions(+)
> 
> diff --git a/tools/perf/util/annotate-arch/annotate-arm64.c b/tools/perf/util/annotate-arch/annotate-arm64.c
> index 151184210691..a7595a954cfa 100644
> --- a/tools/perf/util/annotate-arch/annotate-arm64.c
> +++ b/tools/perf/util/annotate-arch/annotate-arm64.c
> @@ -14,6 +14,7 @@ struct arch_arm64 {
>  	struct arch arch;
>  	regex_t call_insn;
>  	regex_t jump_insn;
> +	regex_t ldst_insn; /* load and store instruction */
>  };
>  
>  static bool arm64__is_reg(const char *op)
> @@ -170,6 +171,130 @@ static const struct ins_ops arm64_mov_ops = {
>  	.scnprintf = arm64_mov__scnprintf,
>  };
>  
> +static bool arm64__insn_is_target_on_right(const char *ins_name)
> +{
> +	/*
> +	 * Store instructions write to the memory operand on the right,
> +	 * unlike standard syntax where the target is the left operand.
> +	 */
> +	return !strncmp(ins_name, "st", 2);
> +}
> +
> +/*
> + * This function is used to parse arm64 load/store instructions into
> + * instruction operands.
> + *
> + * Typical instructions and their parsing logic:
> + *
> + * 1. Immediate offset:
> + *    ldr   x2, [x0]                -> target="x2", source="[x0]"
> + *    ldr   x2, [x0, #24]           -> target="x2", source="[x0, #24]"
> + *    ldp   x19, x20, [sp, #16]     -> target="x19, x20", source="[sp, #16]"
> + *
> + * 2. Pre-index addressing:
> + *    stp   x29, x30, [sp, #-64]!   -> target="[sp, #-64]!", source="x29, x30"
> + *
> + * 3. Post-index addressing:
> + *    str   x1, [x0], #8            -> target="[x0], #8", source="x1"
> + *    ldr   w1, [x21], #4           -> target="w1", source="[x21], #4"
> + *    ldp   x29, x30, [sp], #32     -> target="x29, x30", source="[sp], #32"
> + *
> + * 4. Register offset / extension:
> + *    ldr   x0, [x1, w0, sxtw #3]   -> target="x0", source="[x1, w0, sxtw #3]"
> + *    ldr   x0, [x1, x0, lsl #3]    -> target="x0", source="[x1, x0, lsl #3]"
> + *
> + * 5. Atomic operations:
> + *    cas   w3, w1, [x0]            -> target="w3, w1", source="[x0]"
> + *    swp   x3, x0, [x2]            -> target="x3, x0", source="[x2]"
> + *
> + * 6. Prefetch memory:
> + *    prfm  pstl1strm, [x4]         -> target="pstl1strm", source="[x4]"
> + *
> + * 7. PC-relative loads (No bracket found):
> + *    ldr   x0, ffff800080f40c68 <__kvm_nvhe_$d>  -> Fallback to default parser
> + *
> + * Parsing strategy:
> + * Use the '[' bracket as the boundary to split the operands into left
> + * and right sides. For non-store instructions, the left side is the
> + * target and the right side is the source. For store instructions, the
> + * roles are reversed.
> + */
> +static int arm64_ldst__parse(const struct arch *arch, struct ins_operands *ops,
> +			     struct map_symbol *ms, struct disasm_line *dl)
> +{
> +	char *raw, *s, *left, *right;
> +	int ret = -1;
> +
> +	raw = rstrip_space_and_comment(ops->raw, arch->objdump.comment_char);
> +	if (!raw)
> +		return -1;
> +
> +	s = strchr(raw, arch->objdump.memory_ref_char);
> +	if (!s) {
> +		/* Fallback to default parser for PC-relative loads. */
> +		free(raw);
> +		return arm64_mov__parse(arch, ops, ms, dl);
> +	}
> +
> +	right = strdup(s);
> +	if (!right)
> +		goto out_free_raw;
> +
> +	while (s > raw && *s != ',')
> +		--s;
> +
> +	if (s == raw)
> +		goto out_free_right;
> +
> +	*s = '\0';
> +	left = strdup(raw);
> +	*s = ',';
> +	if (!left)
> +		goto out_free_right;
> +
> +	free(raw);
> +
> +	if (arm64__insn_is_target_on_right(dl->ins.name)) {
> +		ops->source.raw = left;
> +		ops->source.mem_ref = false;
> +
> +		ops->target.raw = right;
> +		ops->target.mem_ref = true;
> +	} else {
> +		ops->source.raw = right;
> +		ops->source.mem_ref = true;
> +
> +		ops->target.raw = left;
> +		ops->target.mem_ref = false;
> +	}
> +
> +	ops->source.multi_regs = arm64__check_multi_regs(arch, ops->source.raw);
> +	ops->target.multi_regs = arm64__check_multi_regs(arch, ops->target.raw);
> +
> +	return 0;
> +
> +out_free_right:
> +	free(right);
> +out_free_raw:
> +	free(raw);
> +	return ret;
> +}
> +
> +static int arm64_ldst__scnprintf(const struct ins *ins, char *bf, size_t size,
> +				 struct ins_operands *ops, int max_ins_name)
> +{
> +	if (arm64__insn_is_target_on_right(ins->name))
> +		return scnprintf(bf, size, "%-*s %s", max_ins_name, ins->name, ops->raw);
> +
> +	return scnprintf(bf, size, "%-*s %s, %s", max_ins_name, ins->name,
> +			 ops->target.raw, ops->source.name ?: ops->source.raw);
> +}
> +
> +static struct ins_ops arm64_ldst_ops = {
> +	.parse	   = arm64_ldst__parse,
> +	.scnprintf = arm64_ldst__scnprintf,
> +};
> +
>  static const struct ins_ops *arm64__associate_instruction_ops(struct arch *arch, const char *name)
>  {
>  	struct arch_arm64 *arm = container_of(arch, struct arch_arm64, arch);
> @@ -180,6 +305,8 @@ static const struct ins_ops *arm64__associate_instruction_ops(struct arch *arch,
>  		ops = &jump_ops;
>  	else if (!regexec(&arm->call_insn, name, 2, match, 0))
>  		ops = &call_ops;
> +	else if (!regexec(&arm->ldst_insn, name, 2, match, 0))
> +		ops = &arm64_ldst_ops;
>  	else if (!strcmp(name, "ret"))
>  		ops = &ret_ops;
>  	else
> @@ -205,6 +332,7 @@ const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id,
>  	arch->objdump.comment_char	  = '/';
>  	arch->objdump.skip_functions_char = '+';
>  	arch->objdump.memory_ref_char	  = '[';
> +	arch->objdump.imm_char		  = '#';
>  	arch->associate_instruction_ops   = arm64__associate_instruction_ops;
>  
>  	/* bl, blr */
> @@ -218,8 +346,20 @@ const struct arch *arch__new_arm64(const struct e_machine_and_e_flags *id,
>  	if (err)
>  		goto out_free_call;
>  
> +	/*
> +	 * The ARM64 architecture has many variants of load/store instructions.
> +	 * It is quite challenging to match all of them completely. Here, we
> +	 * only match the prefixes of these instructions.
> +	 */
> +	err = regcomp(&arm->ldst_insn, "^(ld|st|cas|prf|swp)",
> +		      REG_EXTENDED);
> +	if (err)
> +		goto out_free_jump;
> +
>  	return arch;
>  
> +out_free_jump:
> +	regfree(&arm->jump_insn);
>  out_free_call:
>  	regfree(&arm->call_insn);
>  out_free_arm:
> -- 
> 2.34.1
>