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From: Lukas Wunner <lukas@wunner.de>
To: Terry Bowman <terry.bowman@amd.com>
Cc: Jonathan Cameron <jic23@kernel.org>,
	Dave Jiang <dave.jiang@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dan Williams <djbw@kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-cxl@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
	Borislav Petkov <bp@alien8.de>, Hanjun Guo <guohanjun@huawei.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Shuai Xue <xueshuai@linux.alibaba.com>,
	Len Brown <lenb@kernel.org>, Ira Weiny <iweiny@kernel.org>,
	Li Ming <ming.li@zohomail.com>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Ben Cheatham <Benjamin.Cheatham@amd.com>,
	Richard Cheng <icheng@nvidia.com>,
	Robert Richter <rrichter@amd.com>,
	linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v20 6/9] PCI: Cache PCI DSN into pci_dev->dsn during probe
Date: Wed, 9 Sep 2026 17:16:14 +0200	[thread overview]
Message-ID: <aqF4PqdWtKpecQc2@wunner.de> (raw)
In-Reply-To: <20260902133933.2992457-7-terry.bowman@amd.com>

On Wed, Sep 02, 2026 at 08:39:30AM -0500, Terry Bowman wrote:
> Subsequent CXL error-reporting code paths need to log the PCI Device
> Serial Number (DSN) as part of trace events emitted from interrupt or
> panic context. Computing the DSN there via pci_get_dsn() requires PCI
> configuration space reads, which are slow, can fail when the link is
> down or frozen, and may not be safe in some contexts.
> 
> Add a u64 dsn field to struct pci_dev and populate it from pci_get_dsn()
> during pci_init_capabilities() at probe time via pci_dsn_init(). Only
> write dev->dsn when the read succeeds. The zero initial value from
> pci_dev allocation already represents 'no DSN available.'
[...]
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>

Reviewed-by: Lukas Wunner <lukas@wunner.de>

> +++ b/drivers/pci/probe.c
> @@ -2638,6 +2638,22 @@ void pcie_report_downtraining(struct pci_dev *dev)
>  	__pcie_print_link_status(dev, false);
>  }
>  
> +/*
> + * Cache the Device Serial Number for use in contexts where config-space reads
> + * are unsafe (interrupt, panic). Process-context callers that need a fresh
> + * value (e.g. hotplug device replacement) call pci_get_dsn() and compare it
> + * against this cached pdev->dsn to detect a changed device. Note pdev->dsn
> + * is 0 for devices without the DSN capability, so such a comparison cannot
> + * distinguish a replacement.
> + */

A value of 0 is not a valid serial number in the first place:

PCIe r7.0 sec 7.9.3.2 defines the Device Serial Number as an EUI-64.

In the corresponding IEEE spec on EUIs on page 11 in section
"Unassigned and NULL EUI values", it says:

   "Many applications have found it useful to define a distinct null
    identifier, most often indicating the absence of a valid EUI-48 or
    EUI-64 value. As an example, a null value might be the power-on state
    for an integrated circuit register, until the hardware or firmware
    initializes the register with a valid EUI.
    [...]
    The all-zeros EUI-48 value (00-00-00-00-00-00) and EUI-64 value
    (00-00-00-00-00-00-00-00), though assigned to an organization,
    have not been and will not be used by that assignee as an EUI.
    (They can be considered as assigned to the IEEE Registration Authority.)"

    https://standards.ieee.org/content/dam/ieee-standards/standards/web/documents/tutorials/eui.pdf

Thanks,

Lukas

  parent reply	other threads:[~2026-09-09 15:16 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02 13:39 [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-09-02 13:39 ` [PATCH v20 1/9] PCI/AER: Introduce AER-CXL protocol error kfifo Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-08  0:51   ` Jonathan Cameron
2026-09-09 15:38     ` Bowman, Terry
2026-09-09 22:02       ` Jonathan Cameron
2026-09-10 14:57         ` Bowman, Terry
2026-09-02 13:39 ` [PATCH v20 2/9] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-10 16:55     ` Bowman, Terry
2026-09-08  0:57   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 3/9] cxl/ras: Handle RCH correctable and uncorrectable errors in one pass Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-08  1:06   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 4/9] cxl/pci: Thread port and dport through RAS handling helpers Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-09 14:42     ` Bowman, Terry
2026-09-09 15:21     ` Bowman, Terry
2026-09-08 17:47   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 5/9] cxl: Update CXL Endpoint AER handler Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 6/9] PCI: Cache PCI DSN into pci_dev->dsn during probe Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-09 15:16   ` Lukas Wunner [this message]
2026-09-02 13:39 ` [PATCH v20 7/9] cxl: Add port and dport identifiers to CXL AER trace events Terry Bowman
2026-09-08 18:13   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 8/9] PCI/CXL: Mask/Unmask CXL protocol errors Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 9/9] Documentation: cxl: Document CXL protocol error handling Terry Bowman
2026-09-08 18:39   ` Jonathan Cameron
2026-09-10 15:19     ` Bowman, Terry
2026-09-09 16:03 ` [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Lukas Wunner
2026-09-09 20:31   ` Bowman, Terry

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