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From: Lukas Wunner <lukas@wunner.de>
To: Terry Bowman <terry.bowman@amd.com>
Cc: Jonathan Cameron <jic23@kernel.org>,
	Dave Jiang <dave.jiang@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dan Williams <djbw@kernel.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Jonathan Corbet <corbet@lwn.net>,
	linux-cxl@vger.kernel.org, Tony Luck <tony.luck@intel.com>,
	Borislav Petkov <bp@alien8.de>, Hanjun Guo <guohanjun@huawei.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Shuai Xue <xueshuai@linux.alibaba.com>,
	Len Brown <lenb@kernel.org>, Ira Weiny <iweiny@kernel.org>,
	Li Ming <ming.li@zohomail.com>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Ben Cheatham <Benjamin.Cheatham@amd.com>,
	Richard Cheng <icheng@nvidia.com>,
	Robert Richter <rrichter@amd.com>,
	linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging
Date: Wed, 9 Sep 2026 18:03:35 +0200	[thread overview]
Message-ID: <aqGDV2GQEqxg_1gE@wunner.de> (raw)
In-Reply-To: <20260902133933.2992457-1-terry.bowman@amd.com>

On Wed, Sep 02, 2026 at 08:39:24AM -0500, Terry Bowman wrote:
> Today the kernel handles native CXL.cachemem RAS only for Endpoints and
> Restricted CXL Host (RCH) Downstream Ports. Root Ports, Upstream Switch
> Ports, and Downstream Switch Ports are uncovered. This series introduces
> a unified CXL protocol error path for all CXL device types, in both VH
> and RCH topologies.

I'm trying to make sense of the existing code.  I know this wasn't
introduced by you (but by Robert in 0a867568bb0d), but you've moved
this code around recently and are extending it in this series.

Errors of the RCH downstream port are signaled as internal errors
of an RCEC on the root bus.  Their handling was plumbed into:

aer_process_err_devices()
  handle_error_source()
    cxl_rch_handle_error()

First of all, handle_error_source() calls pci_aer_handle_error(),
which (for Fatal Errors) will issue an FLR of the RCEC.  Note that
Uncorrectable Internal Errors have Fatal severity by default
(PCIe r7.0 sec 7.8.4.4).

If the Uncorrectable Internal Error was the only error, then why is the
RCEC being reset?  It's just serving as a conduit to inform that there
are CXL errors at the downstream port.  There's no reason at all to
issue an FLR to the RCEC in that case.

Second, cxl_rch_handle_error() then walks all the RCiEPs reporting to
the RCEC.  This also looks weird to me.  Can there ever be more than
one RCiEP?  I think not, but maybe I'm missing something.  If there's
only ever a single RCiEP reporting to the RCEC, why perform a walk?

What we actually want to do is retrieve the CXL errors from the
downstream port's RCRB, but this is done in a fairly roundabout way:
cxl_rch_handle_error() walks the RCiEPs (aka RCDs), invokes the
->error_detected() callback for each, which is cxl_error_detected().
That will then call cxl_handle_rdport_errors() to find the RCH
downstream port to which the RCD is attached.

Isn't there a simpler way to find the RCH downstream port from which
the error originated?  Why do we have to go through the RCDs?

Also, putting this in cxl_error_detected() has a weird side effect:
The function is also invoked when the RCD upstream port experienced
an error.  But because the retrieval, reporting and handling of
RCH downstream port errors was put into this function, those errors
are reported and handled as a side effect of RCD upstream port errors.
What sense does this make?

The commit message of 0a867568bb0d provides the following hint as
to why this approach was chosen:

    The reason for choosing this implementation is that the AER service
    driver claims the RCEC device, but does not allow it to register a
    custom specific handler to support CXL. Connecting the RCEC hard-wired
    with a CXL handler does not work, as the CXL subsystem might not be
    present all the time.

So I think the point may have been to make this work even if the cxl
module is not loaded?  Is that all?  Is that the only reason?
We have try_module_get() and symbol_get() helpers.  You could just
call those prior to invoking functions implemented by the cxl module
from the AER driver.  There's plenty of precedent for that in the kernel.

The problem is that the present approach is fairly complex and has
side effects which make it difficult to understand and reason about
the error handling.  In my view, this should be cleaned up first
before bolting more functionality on top of it.

Thanks,

Lukas

  parent reply	other threads:[~2026-09-09 16:03 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-02 13:39 Terry Bowman
2026-09-02 13:39 ` [PATCH v20 1/9] PCI/AER: Introduce AER-CXL protocol error kfifo Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-08  0:51   ` Jonathan Cameron
2026-09-09 15:38     ` Bowman, Terry
2026-09-09 22:02       ` Jonathan Cameron
2026-09-10 14:57         ` Bowman, Terry
2026-09-02 13:39 ` [PATCH v20 2/9] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-10 16:55     ` Bowman, Terry
2026-09-08  0:57   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 3/9] cxl/ras: Handle RCH correctable and uncorrectable errors in one pass Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-08  1:06   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 4/9] cxl/pci: Thread port and dport through RAS handling helpers Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-09 14:42     ` Bowman, Terry
2026-09-09 15:21     ` Bowman, Terry
2026-09-08 17:47   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 5/9] cxl: Update CXL Endpoint AER handler Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 6/9] PCI: Cache PCI DSN into pci_dev->dsn during probe Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-09 15:16   ` Lukas Wunner
2026-09-02 13:39 ` [PATCH v20 7/9] cxl: Add port and dport identifiers to CXL AER trace events Terry Bowman
2026-09-08 18:13   ` Jonathan Cameron
2026-09-02 13:39 ` [PATCH v20 8/9] PCI/CXL: Mask/Unmask CXL protocol errors Terry Bowman
2026-09-02 20:57   ` Cheatham, Benjamin
2026-09-02 13:39 ` [PATCH v20 9/9] Documentation: cxl: Document CXL protocol error handling Terry Bowman
2026-09-08 18:39   ` Jonathan Cameron
2026-09-10 15:19     ` Bowman, Terry
2026-09-09 16:03 ` Lukas Wunner [this message]
2026-09-09 20:31   ` [PATCH v20 0/9] Enable CXL PCIe Port Protocol Error handling and logging Bowman, Terry

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