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* linux-next: manual merge of the amdgpu tree with the drm-misc,drm-fixes tree
@ 2026-09-11 13:25 Mark Brown
  2026-09-11 15:09 ` Mark Brown
  2026-09-14 23:08 ` Nathan Chancellor
  0 siblings, 2 replies; 5+ messages in thread
From: Mark Brown @ 2026-09-11 13:25 UTC (permalink / raw)
  To: Alex Deucher
  Cc: Alex Deucher, Alex Huang, Alex Hung, Alvin Lee,
	Arunpravin Paneer Selvam, Bhawanpreet Lakha, Dillon Varone,
	Dr. David Alan Gilbert, Fangzhi Zuo, Feifei Xu, Harry Wentland,
	Ivan Lipski, James Lin, Linux Kernel Mailing List,
	Linux Next Mailing List, Maarten Lankhorst, Mario Limonciello,
	Michel Dänzer, Ray Wu, Rodrigo Vivi, Satyajit Roy,
	Thomas Hellström, Timur Kristóf, Tomasz Pakuła,
	Tom Chung, Wenjing Liu, YiPeng Chai

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Hi all,

Today's linux-next merge of the amdgpu tree got conflicts in:

  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.h
  drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c

between commits:

  cfdcf5571c310 ("drm/amd/display: Consult MCCS FreeSync cap only if requested & supported")
  87ceb8cba73d0 ("drm/amdgpu: skip the VMID 0 flush for VRAM")
  7fca7acd60a22 ("drm/amd/display: Honor Broadcast RGB for BT.2020 RGB output")
  bd4f284df04d7 ("drm/amdgpu: Wire up dmem cgroup reclaim for VRAM manager")
  f65198b3d0738 ("drm/amd/display: Use HDMI FreeSync range from common EDID parser")
  ee28f3446dde3 ("drm/amd/display: Clean up FreeSync capability detection")
  ef2e8220c9644 ("drm/amd/display: Check actual state during commit_tail")
  730c6d8072d8d ("drm/amd/display: Drop KUnit tests for removed parse_hdmi_amd_vsdb()")

from the drm-misc,drm-fixes tree and commits:

  7ea37c0f06787 ("drm/amd/display: Force FreeSync range minimum on quirky panels")
  dd7f86c389aea ("drm/amd/display: Update dcn60 clkmgr interfaces")
  ab07c95defdd9 ("drm/amd/display: Apply workaround to limit SopCount for now")
  48c4aaeef6219 ("drm/amdgpu/ttm: Make buffer copy source readonly")
  762e89c63a388 ("drm/amd/display: Guard against empty DCN6 UTM QoS table")
  b5b05ce478a10 ("drm/amd/display: Rename carried dce clock manager functions for dcn10")
  ecaca20be81ce ("drm/amdgpu: Remove is_idle (trivial cases)")
  b7146153a6754 ("drm/amdgpu: Add bad page preloading and pre-reservation support")
  e3d5618d4dad3 ("drm/amd/display: Test GPU memory allocation")
  985c7177f630c ("drm/amd/display: Cover amdgpu_dm_encoder_init")
  01678168f9d55 ("drm/amd/display: Cover amdgpu_dm_connector_atomic_check")
  0d3ff9e9bbbc7 ("drm/amd/display: Cover amdgpu_dm_connector_get_modes")
  889f15060c3da ("drm/amd/display: Cover amdgpu_set_panel_orientation")
  5113a08a4ba47 ("drm/amd/display: Cover amdgpu_dm_prune_primary_tile_modes")
  11b7722b8ac69 ("drm/amd/display: Refactor hdmi_frl_status_polling_work for Kunit testing")
  4827661d374b9 ("drm/amd/display: Cover hdmi_frl_status_polling_work")
  8dade94422319 ("drm/amd/display: Cover amdgpu_dm_create_i2c")
  2eee94d2e09e4 ("drm/amdgpu: query the reserved info with get_fw_reserved_info")
  1f47aaf3ff0d8 ("drm/amd/display: Add HDMI 2.1 FreeSync support for AMD VSDB")
  fa3389c713799 ("drm/amd/display: Add HDMI 2.1 VRR support for HF-VSDB")
  8982d9555267a ("drm/amd/display: Guard DAL port idle optimizations by ASIC rev")
  9f915dcc9f1a7 ("drm/amd/display: Test DM atomic private state helpers")
  c8130c0538f08 ("drm/amd/display: Test affected MST DSC CRTC selection")
  1903ffbca1b1b ("drm/amd/display: Test cursor commit")
  b56e334dbd557 ("drm/amd/display: Test vblank event arming")
  0e956130a2705 ("drm/amd/display: Test page flip interrupt state update")
  3bc69baf5e153 ("drm/amd/display: Test CRTC memory domain change detection")
  9885f7d5bd6fb ("drm/amd/display: Test PSR dirty rectangle filling")
  d0f8af4787d0a ("drm/amd/display: Test plane reset decision")
  334a9a3bf317e ("drm/amd/display: Test link and sink dump")
  448defc23908c ("drm/amd/display: Test HDCP update")
  00eaae7bca217 ("drm/amd/display: Add override capability for UTM table params")
  094901372adc0 ("drm/amd/display: Dump clock registers in HW init instead of SW init")
  022236eaa63bb ("drm/amd/display: Honor Broadcast RGB for BT.2020 RGB output")
  0412b1064a3bd ("drm/amd/display: Cover EDID CEA parsing helpers")

from the amdgpu tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 016957cac1f29,0e313d7916a4b..0000000000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 774028dd9ff48,c99a84bb040e5..0000000000000
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
index e2e76e56edb5b,676046ea2da1d..0000000000000
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.c
@@@ -3717,43 -3902,95 +3872,111 @@@ void amdgpu_dm_update_freesync_caps(str
  	     connector->display_info.monitor_range.max_vfreq == 0))
  		parse_edid_displayid_vrr(connector, edid);
  
 -	if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
 -		     sink->sink_signal == SIGNAL_TYPE_EDP)) {
 -		if (amdgpu_dm_connector->dc_link &&
 -		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
 -			amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
 -			amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
 -			if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
 -				freesync_capable = true;
 -		}
 +	has_vsdb = get_amd_vsdb(amdgpu_dm_connector, &vsdb_info) != 0;
  
 -		get_amd_vsdb(amdgpu_dm_connector, &vsdb_info);
 +	if (has_vsdb) {
 +		amdgpu_dm_connector->vsdb_info = vsdb_info;
 +
 +		/* copy refresh rate info as long as VSDB advertises FreeSync */
 +		if (vsdb_info.freesync_supported) {
 +			amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
 +			amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
 +
 +			connector->display_info.monitor_range.min_vfreq =
 +				vsdb_info.min_refresh_rate_hz;
 +			connector->display_info.monitor_range.max_vfreq =
 +				vsdb_info.max_refresh_rate_hz;
 +		}
 +	} else {
 +		/* fall back to the base EDID range when there is no VSDB */
 +		amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
 +		amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;
 +	}
 +
 +	if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
 +	    sink->sink_signal == SIGNAL_TYPE_EDP) {
 +		if (amdgpu_dm_connector->dc_link &&
 +		    amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param &&
 +		    amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
 +			freesync_capable = true;
  
  		if (vsdb_info.replay_mode) {
 -			amdgpu_dm_connector->vsdb_info.replay_mode = vsdb_info.replay_mode;
 -			amdgpu_dm_connector->vsdb_info.amd_vsdb_version = vsdb_info.amd_vsdb_version;
  			amdgpu_dm_connector->as_type = ADAPTIVE_SYNC_TYPE_EDP;
  		}
 +	} else if (has_vsdb && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
 +		sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code;
  
- 		if (vsdb_info.freesync_supported &&
- 		    amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
- 			freesync_capable = true;
+ 	} else if (drm_edid &&
+ 		  (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A ||
+ 		   sink->sink_signal == SIGNAL_TYPE_HDMI_FRL)) {
+ 		i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
+ 		if (i >= 0) {
+ 			amdgpu_dm_connector->vsdb_info = vsdb_info;
+ 			sink->edid_caps.freesync_vcp_code = vsdb_info.freesync_mccs_vcp_code;
+ 
+ 			if (vsdb_info.freesync_supported) {
+ 				amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
+ 				amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
+ 				if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
+ 					freesync_capable = true;
+ 
+ 				connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
+ 				connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
+ 			}
+ 		}
+ 
+ 		drm_dbg_driver(adev_to_drm(adev),
+ 			       "VRR: amd_vsdb i=%d fs_sup=%d min=%d max=%d fs_capable=%d\n",
+ 			       i, vsdb_info.freesync_supported,
+ 			       vsdb_info.min_refresh_rate_hz,
+ 			       vsdb_info.max_refresh_rate_hz, freesync_capable);
+ 
+ 		/*
+ 		 * If AMD VSDB didn't provide a valid FreeSync range, fall back to
+ 		 * the HDMI 2.1 VRR capability parsed from the HF-VSDB.
+ 		 */
+ 		if (!freesync_capable && connector->display_info.hdmi.vrr_cap.supported) {
+ 			struct drm_hdmi_vrr_cap *vrr_cap =
+ 				&connector->display_info.hdmi.vrr_cap;
+ 
+ 			drm_dbg_driver(adev_to_drm(adev),
+ 				       "VRR: HF-VSDB fallback: hdmi_vrr=1 vrr_cap[sup=%d min=%d max=%d] mrange_max=%d\n",
+ 				       vrr_cap->supported, vrr_cap->vrr_min, vrr_cap->vrr_max,
+ 				       connector->display_info.monitor_range.max_vfreq);
+ 
+ 			if (vrr_cap->supported && vrr_cap->vrr_min > 0) {
+ 				amdgpu_dm_connector->min_vfreq = vrr_cap->vrr_min;
+ 				amdgpu_dm_connector->max_vfreq = vrr_cap->vrr_max ?
+ 					vrr_cap->vrr_max :
+ 					connector->display_info.monitor_range.max_vfreq;
+ 
+ 				/*
+ 				 * VRRMAX = 0 in the HF-VSDB means "up to the Base
+ 				 * Refresh Rate". If the EDID also did not provide a
+ 				 * monitor range max, fall back to the Base Refresh
+ 				 * Rate (the highest refresh rate of the preferred
+ 				 * timing) so a valid VRR range is still reported to
+ 				 * userspace.
+ 				 */
+ 				if (!amdgpu_dm_connector->max_vfreq) {
+ 					struct drm_display_mode *brr_mode =
+ 						amdgpu_dm_get_highest_refresh_rate_mode(amdgpu_dm_connector, true);
+ 
+ 					if (brr_mode)
+ 						amdgpu_dm_connector->max_vfreq =
+ 							drm_mode_vrefresh(brr_mode);
+ 				}
+ 
+ 				if (amdgpu_dm_connector->max_vfreq -
+ 				    amdgpu_dm_connector->min_vfreq > 10)
+ 					freesync_capable = true;
+ 
+ 				connector->display_info.monitor_range.min_vfreq =
+ 					amdgpu_dm_connector->min_vfreq;
+ 				connector->display_info.monitor_range.max_vfreq =
+ 					amdgpu_dm_connector->max_vfreq;
+ 			}
+ 		}
  	}
  
  	if (amdgpu_dm_connector->dc_link)
diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.h
index ce900844602e5,e42a0d53b549b..0000000000000
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_connector.h
diff --cc drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index 7dd88d90eba2f,138afa7afc861..0000000000000
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c

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^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-09-15 16:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-09-11 13:25 linux-next: manual merge of the amdgpu tree with the drm-misc,drm-fixes tree Mark Brown
2026-09-11 15:09 ` Mark Brown
2026-09-14 23:08 ` Nathan Chancellor
2026-09-14 23:19   ` Mark Brown
2026-09-15 16:39   ` Mark Brown

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