[PATCH v5 00/42] clk: qcom: Tie CX power domains to GCCs

[PATCH v5 00/42] clk: qcom: Tie CX power domains to GCCs

[Abel Vesa]

Tie the CX power domain to GCC clock controllers for SDM670,
SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
SM4450, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
X1E80100, Eliza, Kaanapali, and QCS615.

Enable runtime PM for GCC providers without critical clocks, allowing CX to
power down when their consumers release clocks and GDSCs.

On SDM845, the DT already describes the CX as power domain for GCC,
only the driver needs runtime PM enabling.

Update the GCC bindings to document and require the CX power-domain
dependency for the affected compatibles.

Only Kaanapali and Eliza require Fixes tags, as runtime PM support was not
available when the other platforms were upstreamed.

---
Changes in v5:
- Rebased on next-20260922.
- Drop QDU1000: its CX rail is always at NOMINAL and does not follow
  the regular PMIC control.
- Require the CX power domain at the binding top level for SDM670 and
  SDM845.
- Pick up Krzysztof's R-b tags for the DT bindings and Taniya's R-b
  tag for SC7280 GCC.
- Drop runtime PM enablement for providers with critical clocks, which keep
  the controller active.
- Link to v4: https://patch.msgid.link/20260914-qcom-tie-cx-to-gcc-v4-0-9d5a606ada33@oss.qualcomm.com

Changes in v4:
- Rebased on next-20260911.
- Add missing CX power-domain bindings for QCS8300, QDU1000, SDX75, SM4450, and SM6350.
- Address Krzysztof's binding review by documenting the CX power-domain item.
- Explain why the new required property is needed to prevent CX undervolting.
- Include the direct RPMh power-domain header in binding examples.
- Link to v3: https://patch.msgid.link/20260824-qcom-tie-cx-to-gcc-v3-0-f1205a92682b@oss.qualcomm.com

Changes in v2:
- Clarify the runtime PM rationale in the GCC driver commit messages.
- Picked up Konrad's R-b tag for the dts patches.
- Link to v1: https://patch.msgid.link/20260819-qcom-tie-cx-to-gcc-v1-0-840034124e73@oss.qualcomm.com

To: Bjorn Andersson <andersson@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>
To: Brian Masney <bmasney+clk@redhat.com>
To: Jerome Brunet <jbrunet+clk@baylibre.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Taniya Das <taniya.das@oss.qualcomm.com>
To: Vinod Koul <vkoul@kernel.org>
To: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
To: Abel Vesa <abel.vesa@oss.qualcomm.com>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Tengfei Fan <tengfei.fan@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzk@kernel.org>

---
Abel Vesa (42):
      dt-bindings: clock: qcom: gcc-sdm845: Require CX power domain
      dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain
      dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain
      dt-bindings: clock: qcom: sm4450-gcc: Add CX power domain
      dt-bindings: clock: qcom: gcc-sm6350: Add CX power domain
      dt-bindings: clock: qcom: qcs8300-gcc: Add CX power domain
      dt-bindings: clock: qcom: sdx75-gcc: Add CX power domain
      clk: qcom: gcc-eliza: Tie the CX power domain to controller
      clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
      clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
      clk: qcom: gcc-sa8775p: Tie the CX power domain to controller
      clk: qcom: gcc-sar2130p: Tie the CX power domain to controller
      clk: qcom: gcc-sc7280: Tie the CX power domain to controller
      clk: qcom: gcc-sdx75: Tie the CX power domain to controller
      clk: qcom: gcc-sm4450: Tie the CX power domain to controller
      clk: qcom: gcc-sm8350: Tie the CX power domain to controller
      clk: qcom: gcc-sm8450: Tie the CX power domain to controller
      clk: qcom: gcc-sm8550: Tie the CX power domain to controller
      clk: qcom: gcc-sm8650: Tie the CX power domain to controller
      clk: qcom: gcc-sm8750: Tie the CX power domain to controller
      clk: qcom: gcc-x1e80100: Tie the CX power domain to controller
      arm64: dts: qcom: kaanapali: Add GCC CX power domain
      arm64: dts: qcom: monaco: Add GCC CX power domain
      arm64: dts: qcom: sar2130p: Add GCC CX power domain
      arm64: dts: qcom: sdm670: Add GCC CX power domain
      arm64: dts: qcom: sdx75: Add GCC CX power domain
      arm64: dts: qcom: sm4450: Add GCC CX power domain
      arm64: dts: qcom: sm6350: Add GCC CX power domain
      arm64: dts: qcom: sm8150: Add GCC CX power domain
      arm64: dts: qcom: sm8250: Add GCC CX power domain
      arm64: dts: qcom: sm8350: Add GCC CX power domain
      arm64: dts: qcom: sm8450: Add GCC CX power domain
      arm64: dts: qcom: sm8550: Add GCC CX power domain
      arm64: dts: qcom: sm8650: Add GCC CX power domain
      arm64: dts: qcom: sm8750: Add GCC CX power domain
      arm64: dts: qcom: talos: Add GCC CX power domain

 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml  | 6 +++++-
 Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml   | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml  | 7 +++++++
 Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml  | 7 +++++++
 arch/arm64/boot/dts/qcom/kaanapali.dtsi                       | 2 ++
 arch/arm64/boot/dts/qcom/monaco.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sar2130p.dtsi                        | 1 +
 arch/arm64/boot/dts/qcom/sdm670.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sdx75.dtsi                           | 1 +
 arch/arm64/boot/dts/qcom/sm4450.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm6350.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8150.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8250.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8350.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8450.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8550.dtsi                          | 1 +
 arch/arm64/boot/dts/qcom/sm8650.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/sm8750.dtsi                          | 2 ++
 arch/arm64/boot/dts/qcom/talos.dtsi                           | 2 ++
 drivers/clk/qcom/gcc-eliza.c                                  | 1 +
 drivers/clk/qcom/gcc-kaanapali.c                              | 1 +
 drivers/clk/qcom/gcc-qcs8300.c                                | 1 +
 drivers/clk/qcom/gcc-sa8775p.c                                | 1 +
 drivers/clk/qcom/gcc-sar2130p.c                               | 1 +
 drivers/clk/qcom/gcc-sc7280.c                                 | 1 +
 drivers/clk/qcom/gcc-sdx75.c                                  | 1 +
 drivers/clk/qcom/gcc-sm4450.c                                 | 1 +
 drivers/clk/qcom/gcc-sm8350.c                                 | 1 +
 drivers/clk/qcom/gcc-sm8450.c                                 | 1 +
 drivers/clk/qcom/gcc-sm8550.c                                 | 1 +
 drivers/clk/qcom/gcc-sm8650.c                                 | 1 +
 drivers/clk/qcom/gcc-sm8750.c                                 | 1 +
 drivers/clk/qcom/gcc-x1e80100.c                               | 1 +
 42 files changed, 122 insertions(+), 1 deletion(-)
---
base-commit: a8c591ed6b672915e0be57843f943a2a723aff40
change-id: 20260819-qcom-tie-cx-to-gcc-67e6697639b5

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH v5 01/42] dt-bindings: clock: qcom: gcc-sdm845: Require CX power domain

[Abel Vesa]

Require the CX power-domain dependency for SDM845 and SDM670 GCCs.

Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
index a7523a414341..41767eb11651 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
@@ -31,11 +31,13 @@ properties:
     maxItems: 5
 
   power-domains:
-    maxItems: 1
+    items:
+      - description: CX power domain
 
 required:
   - compatible
   - '#power-domain-cells'
+  - power-domains
 
 allOf:
   - $ref: qcom,gcc.yaml#
@@ -85,6 +87,7 @@ examples:
   # Example for GCC for SDM845:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sdm845";
       reg = <0x100000 0x1f0000>;
@@ -94,6 +97,7 @@ examples:
                <&pcie0_lane>,
                <&pcie1_lane>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk";
+      power-domains = <&rpmhpd SDM845_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 02/42] dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain

[Abel Vesa]

Describe the CX power-domain dependency for SM8150 GCC and require it in
the binding.

Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
index 5f3f69fe9ddb..82d67b0d82d0 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
@@ -30,10 +30,15 @@ properties:
       - const: bi_tcxo
       - const: sleep_clk
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -44,12 +49,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8150";
       reg = <0x00100000 0x1f0000>;
       clocks = <&rpmhcc RPMH_CXO_CLK>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd SM8150_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 03/42] dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8250 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
index f4cd5a509c60..5f9aae728245 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
@@ -32,10 +32,15 @@ properties:
       - const: bi_tcxo_ao
       - const: sleep_clk
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -46,6 +51,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8250";
       reg = <0x00100000 0x1f0000>;
@@ -53,6 +59,7 @@ examples:
                <&rpmhcc RPMH_CXO_CLK_A>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 04/42] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8350 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
index 97ffae3b5522..7f3947db5807 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
@@ -51,10 +51,15 @@ properties:
       - const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
     minItems: 2
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -65,12 +70,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8350";
       reg = <0x00100000 0x1f0000>;
       clocks = <&rpmhcc RPMH_CXO_CLK>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 05/42] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8450 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
index 3169ac05e1d8..793ee9e3ff10 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
@@ -47,10 +47,15 @@ properties:
       - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
     minItems: 2
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -61,11 +66,13 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm8450";
       reg = <0x00100000 0x001f4200>;
       clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
       clock-names = "bi_tcxo", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 06/42] dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the QCS615 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
index 4a828e102d25..c87248531563 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml
@@ -31,10 +31,15 @@ properties:
       - const: bi_tcxo_ao
       - const: sleep_clk
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -45,6 +50,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,qcs615-gcc";
       reg = <0x00100000 0x1f0000>;
@@ -52,6 +58,7 @@ examples:
                <&rpmhcc RPMH_CXO_CLK_A>,
                <&sleep_clk>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 07/42] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8550 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
index c4e9b9bb63f5..f9423aff5dea 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
@@ -31,9 +31,14 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -44,6 +49,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8550-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -55,6 +61,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 08/42] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8650 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
index c7143e2abc80..543105b277d5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
@@ -32,9 +32,14 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -45,6 +50,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8650-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -58,6 +64,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 09/42] dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM8750 and Kaanapali GCCs are supplied by the
RPMh CX power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.

Fixes: 342d2a607450 ("dt-bindings: clock: qcom: Add Kaanapali Global clock controller")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
index 0114d347b26f..59da3eb2b073 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
@@ -34,9 +34,14 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -47,6 +52,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm8750-gcc";
       reg = <0x00100000 0x001f4200>;
@@ -58,6 +64,7 @@ examples:
                <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>,
                <&usb_1_qmpphy>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 10/42] dt-bindings: clock: qcom: sm4450-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM4450 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
index 9cfe859bacc9..e143300e7be9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
@@ -29,9 +29,14 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -42,12 +47,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,sm4450-gcc";
       reg = <0x00100000 0x001f4200>;
       clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
                <&ufs_mem_phy 0>, <&ufs_mem_phy 1>,
                <&ufs_mem_phy 2>, <&usb_1_qmpphy>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 11/42] dt-bindings: clock: qcom: gcc-sm6350: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SM6350 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
index 819e855eaf9a..098a108b8123 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
@@ -31,10 +31,15 @@ properties:
       - const: bi_tcxo_ao
       - const: sleep_clk
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
   - clock-names
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -45,12 +50,14 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,gcc-sm6350";
       reg = <0x00100000 0x1f0000>;
       clocks = <&rpmhcc RPMH_CXO_CLK>,
                <&rpmhcc RPMH_CXO_CLK_A>,
                <&sleep_clk>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
       #clock-cells = <1>;
       #reset-cells = <1>;

-- 
2.54.0

[PATCH v5 12/42] dt-bindings: clock: qcom: qcs8300-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the QCS8300 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml
index 081bc452081f..a2f6e97f1848 100644
--- a/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml
@@ -33,9 +33,14 @@ properties:
       - description: UFS Phy Tx symbol 0 clock source
       - description: USB3 Phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -46,6 +51,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@100000 {
       compatible = "qcom,qcs8300-gcc";
       reg = <0x00100000 0xc7018>;
@@ -59,6 +65,7 @@ examples:
                <&ufs_phy_rx_symbol_1_clk>,
                <&ufs_phy_tx_symbol_0_clk>,
                <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 13/42] dt-bindings: clock: qcom: sdx75-gcc: Add CX power domain

[Abel Vesa]

The GDSCs provided by the SDX75 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.

Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
index 29a0b29bcb81..75a38e9f3248 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
@@ -38,9 +38,14 @@ properties:
       - description: PCIE Pipe clock source
       - description: USB3 phy wrapper pipe clock source
 
+  power-domains:
+    items:
+      - description: CX power domain
+
 required:
   - compatible
   - clocks
+  - power-domains
   - '#power-domain-cells'
 
 allOf:
@@ -51,6 +56,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom,rpmhpd.h>
     clock-controller@80000 {
       compatible = "qcom,sdx75-gcc";
       reg = <0x80000 0x1f7400>;
@@ -59,6 +65,7 @@ examples:
                <&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
                <&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
                <&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
+      power-domains = <&rpmhpd RPMHPD_CX>;
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 14/42] clk: qcom: gcc-eliza: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Fixes: 6393a36fe184 ("clk: qcom: Add support for Global clock controller on Eliza")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-eliza.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c
index ee486c24fe66..064771726e9b 100644
--- a/drivers/clk/qcom/gcc-eliza.c
+++ b/drivers/clk/qcom/gcc-eliza.c
@@ -3068,6 +3068,7 @@ static const struct qcom_cc_desc gcc_eliza_desc = {
 	.num_resets = ARRAY_SIZE(gcc_eliza_resets),
 	.gdscs = gcc_eliza_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
+	.use_rpm = true,
 	.driver_data = &gcc_eliza_driver_data,
 };
 

-- 
2.54.0

[PATCH v5 15/42] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-kaanapali.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
index e310b5c9b5c7..c9473fb79ccc 100644
--- a/drivers/clk/qcom/gcc-kaanapali.c
+++ b/drivers/clk/qcom/gcc-kaanapali.c
@@ -3502,6 +3502,7 @@ static const struct qcom_cc_desc gcc_kaanapali_desc = {
 	.num_resets = ARRAY_SIZE(gcc_kaanapali_resets),
 	.gdscs = gcc_kaanapali_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs),
+	.use_rpm = true,
 	.driver_data = &gcc_kaanapali_driver_data,
 };
 

-- 
2.54.0

[PATCH v5 16/42] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-qcs8300.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-qcs8300.c b/drivers/clk/qcom/gcc-qcs8300.c
index 57014c4f8c6d..fa57c3989eb1 100644
--- a/drivers/clk/qcom/gcc-qcs8300.c
+++ b/drivers/clk/qcom/gcc-qcs8300.c
@@ -3681,6 +3681,7 @@ static const struct qcom_cc_desc gcc_qcs8300_desc = {
 	.num_resets = ARRAY_SIZE(gcc_qcs8300_resets),
 	.gdscs = gcc_qcs8300_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_qcs8300_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_qcs8300_match_table[] = {

-- 
2.54.0

[PATCH v5 17/42] clk: qcom: gcc-sa8775p: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sa8775p.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index dca316decd0e..2f867596bbc5 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4652,6 +4652,7 @@ static const struct qcom_cc_desc gcc_sa8775p_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sa8775p_resets),
 	.gdscs = gcc_sa8775p_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sa8775p_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sa8775p_match_table[] = {

-- 
2.54.0

[PATCH v5 18/42] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sar2130p.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sar2130p.c b/drivers/clk/qcom/gcc-sar2130p.c
index 7456001cf25e..7a3478a9ffd2 100644
--- a/drivers/clk/qcom/gcc-sar2130p.c
+++ b/drivers/clk/qcom/gcc-sar2130p.c
@@ -2308,6 +2308,7 @@ static const struct qcom_cc_desc gcc_sar2130p_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sar2130p_resets),
 	.gdscs = gcc_sar2130p_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sar2130p_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sar2130p_match_table[] = {

-- 
2.54.0

[PATCH v5 19/42] clk: qcom: gcc-sc7280: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sc7280.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
index e1fe64463de6..45fcfa7600d0 100644
--- a/drivers/clk/qcom/gcc-sc7280.c
+++ b/drivers/clk/qcom/gcc-sc7280.c
@@ -3446,6 +3446,7 @@ static const struct qcom_cc_desc gcc_sc7280_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sc7280_resets),
 	.gdscs = gcc_sc7280_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sc7280_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sc7280_match_table[] = {

-- 
2.54.0

[PATCH v5 20/42] clk: qcom: gcc-sdx75: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sdx75.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sdx75.c b/drivers/clk/qcom/gcc-sdx75.c
index ce9f19655d6d..97be0f47bd18 100644
--- a/drivers/clk/qcom/gcc-sdx75.c
+++ b/drivers/clk/qcom/gcc-sdx75.c
@@ -2913,6 +2913,7 @@ static const struct qcom_cc_desc gcc_sdx75_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sdx75_resets),
 	.gdscs = gcc_sdx75_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sdx75_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sdx75_match_table[] = {

-- 
2.54.0

[PATCH v5 21/42] clk: qcom: gcc-sm4450: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm4450.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 4fb4d43e8582..022b87572b16 100644
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2823,6 +2823,7 @@ static const struct qcom_cc_desc gcc_sm4450_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm4450_resets),
 	.gdscs = gcc_sm4450_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm4450_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm4450_match_table[] = {

-- 
2.54.0

[PATCH v5 22/42] clk: qcom: gcc-sm8350: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8350.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index cc6eb7ca9c03..ab4260f70b54 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3787,6 +3787,7 @@ static const struct qcom_cc_desc gcc_sm8350_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
 	.gdscs = gcc_sm8350_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8350_match_table[] = {

-- 
2.54.0

[PATCH v5 23/42] clk: qcom: gcc-sm8450: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8450.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index d473a95bef92..9f4672277932 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3400,6 +3400,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8450_resets),
 	.gdscs = gcc_sm8450_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8450_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8450_match_table[] = {

-- 
2.54.0

[PATCH v5 24/42] clk: qcom: gcc-sm8550: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8550.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index d83a7bb5356b..fcaa4cd82b71 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3327,6 +3327,7 @@ static const struct qcom_cc_desc gcc_sm8550_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8550_resets),
 	.gdscs = gcc_sm8550_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8550_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8550_match_table[] = {

-- 
2.54.0

[PATCH v5 25/42] clk: qcom: gcc-sm8650: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8650.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index 9fa362f0c447..88d0a9e51045 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3785,6 +3785,7 @@ static const struct qcom_cc_desc gcc_sm8650_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8650_resets),
 	.gdscs = gcc_sm8650_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8650_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8650_match_table[] = {

-- 
2.54.0

[PATCH v5 26/42] clk: qcom: gcc-sm8750: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-sm8750.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-sm8750.c b/drivers/clk/qcom/gcc-sm8750.c
index c08130218efe..14d44c51ca5d 100644
--- a/drivers/clk/qcom/gcc-sm8750.c
+++ b/drivers/clk/qcom/gcc-sm8750.c
@@ -3196,6 +3196,7 @@ static const struct qcom_cc_desc gcc_sm8750_desc = {
 	.num_resets = ARRAY_SIZE(gcc_sm8750_resets),
 	.gdscs = gcc_sm8750_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_sm8750_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_sm8750_match_table[] = {

-- 
2.54.0

[PATCH v5 27/42] clk: qcom: gcc-x1e80100: Tie the CX power domain to controller

[Abel Vesa]

Enable runtime PM for the controller, allowing CX to be powered down
once all GCC consumers have released their clocks and GDSCs.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/clk/qcom/gcc-x1e80100.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index 9402fd7fddb8..b979b7415377 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -7449,6 +7449,7 @@ static const struct qcom_cc_desc gcc_x1e80100_desc = {
 	.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
 	.gdscs = gcc_x1e80100_gdscs,
 	.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
+	.use_rpm = true,
 };
 
 static const struct of_device_id gcc_x1e80100_match_table[] = {

-- 
2.54.0

[PATCH v5 28/42] arm64: dts: qcom: kaanapali: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on Kaanapali are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Fixes: 2eeb5767d53f ("arm64: dts: qcom: Introduce Kaanapali SoC")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 131fd2a16c54..c1528cc8b7b3 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -552,6 +552,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <0>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 29/42] arm64: dts: qcom: monaco: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QCS8300 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/monaco.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 395d32d36844..8478e81c4ada 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -897,6 +897,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_phy>,

-- 
2.54.0

[PATCH v5 30/42] arm64: dts: qcom: sar2130p: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SAR2130P are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sar2130p.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index 2ecead79806c..ceeb9c47093e 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -474,6 +474,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_phy>,

-- 
2.54.0

[PATCH v5 31/42] arm64: dts: qcom: sdm670: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SDM670 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index 5c60ea36f04a..1978a54db23b 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -626,6 +626,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd SDM670_CX>;
 		};
 
 		qfprom: qfprom@784000 {

-- 
2.54.0

[PATCH v5 32/42] arm64: dts: qcom: sdx75: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SDX75 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sdx75.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index 81292850e531..c66f7bd9bf9a 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -486,6 +486,7 @@ gcc: clock-controller@80000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v5 33/42] arm64: dts: qcom: sm4450: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM4450 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm4450.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index bc9c788b92b1..11ab6ed4f655 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -389,6 +389,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <0>,

-- 
2.54.0

[PATCH v5 34/42] arm64: dts: qcom: sm6350: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM6350 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 15d38b7e803c..ded5c3a45891 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -794,6 +794,7 @@ gcc: clock-controller@100000 {
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
+			power-domains = <&rpmhpd SM6350_CX>;
 			clock-names = "bi_tcxo",
 				      "bi_tcxo_ao",
 				      "sleep_clk";

-- 
2.54.0

[PATCH v5 35/42] arm64: dts: qcom: sm8150: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8150 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 94a3b02cb289..397c0142ea57 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -913,6 +913,7 @@ gcc: clock-controller@100000 {
 				      "sleep_clk";
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>;
+			power-domains = <&rpmhpd SM8150_CX>;
 		};
 
 		gpi_dma0: dma-controller@800000 {

-- 
2.54.0

[PATCH v5 36/42] arm64: dts: qcom: sm8250: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8250 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8483a1bc56f4..a90e4f30d39a 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -970,6 +970,7 @@ gcc: clock-controller@100000 {
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&rpmhcc RPMH_CXO_CLK_A>,
 				 <&sleep_clk>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v5 37/42] arm64: dts: qcom: sm8350: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8350 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 100faea925a3..2a7c6621ece2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -698,6 +698,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 				 <0>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v5 38/42] arm64: dts: qcom: sm8450: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8450 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 484ec8ec8c10..1af29c5476e3 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -941,6 +941,7 @@ gcc: clock-controller@100000 {
 				      "ufs_phy_rx_symbol_1_clk",
 				      "ufs_phy_tx_symbol_0_clk",
 				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		gpi_dma2: dma-controller@800000 {

-- 
2.54.0

[PATCH v5 39/42] arm64: dts: qcom: sm8550: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8550 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 23604436add3..9e60836f4064 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1194,6 +1194,7 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
+			power-domains = <&rpmhpd RPMHPD_CX>;
 		};
 
 		ipcc: mailbox@408000 {

-- 
2.54.0

[PATCH v5 40/42] arm64: dts: qcom: sm8650: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8650 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 99509305f970..9cf38a7e0b94 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2018,6 +2018,8 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 41/42] arm64: dts: qcom: sm8750: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on SM8750 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 28cf22da854d..b9e943afc510 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -677,6 +677,8 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

[PATCH v5 42/42] arm64: dts: qcom: talos: Add GCC CX power domain

[Abel Vesa]

The GCC GDSCs on QCS615 are backed by the RPMh CX power domain. Without
describing that parent domain, consumers of GCC-provided GDSCs can enable
their local domain without causing the required CX vote to be held.

Add the CX power-domain reference to the GCC node so votes from GCC GDSC
consumers can propagate to RPMh CX.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/talos.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 531cf41b94dc..860673697f1a 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -705,6 +705,8 @@ gcc: clock-controller@100000 {
 				      "bi_tcxo_ao",
 				      "sleep_clk";
 
+			power-domains = <&rpmhpd RPMHPD_CX>;
+
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

-- 
2.54.0

Re: (subset) [PATCH v5 00/42] clk: qcom: Tie CX power domains to GCCs

[Bjorn Andersson]

On Thu, 24 Sep 2026 13:39:16 +0300, Abel Vesa wrote:
> Tie the CX power domain to GCC clock controllers for SDM670,
> SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
> SM4450, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
> X1E80100, Eliza, Kaanapali, and QCS615.
> 
> Enable runtime PM for GCC providers without critical clocks, allowing CX to
> power down when their consumers release clocks and GDSCs.
> 
> [...]

Applied, thanks!

[01/42] dt-bindings: clock: qcom: gcc-sdm845: Require CX power domain
        commit: 55388f587b3301dffdb30074d00f069d80d29341
[02/42] dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain
        commit: 80d35f528a46b5f1e9777ce83de48fd9efa7c422
[03/42] dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain
        commit: 98e936c9d46a25b4eceacf907fe5d87b3999040e
[04/42] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain
        commit: 534af057998b59a4813fd2eba524f2f523f356d6
[05/42] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain
        commit: 4de0860a340888fd2582681facbceda71b375617
[06/42] dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain
        commit: 779dd957c4c8a7d7d0fd8ac03caa27fe6db23514
[07/42] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain
        commit: 5a577a480dd3d764cc2f55a112efc92d59ad59ec
[08/42] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain
        commit: 76615e10462c425f926e50dce52e9d23bb2f9428
[09/42] dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain
        commit: f9c74b6ed57922b1fdb1ed6835665e06b5ba01a5
[10/42] dt-bindings: clock: qcom: sm4450-gcc: Add CX power domain
        commit: df3faa0e74e433304f9a6f33d3ac4d3376fcdc06
[11/42] dt-bindings: clock: qcom: gcc-sm6350: Add CX power domain
        commit: 3d4f3414300bba79d517585ac10181e285ca6be3
[12/42] dt-bindings: clock: qcom: qcs8300-gcc: Add CX power domain
        commit: fcf1810fede27777f9b708a9cef431bcac1d8e38
[13/42] dt-bindings: clock: qcom: sdx75-gcc: Add CX power domain
        commit: 6df1fd0bfa649c0f13abd026a01dbed5f1727fea
[14/42] clk: qcom: gcc-eliza: Tie the CX power domain to controller
        commit: 4eb8f2ad36888e5b29aa0a5e7e0bc60e382312ea
[15/42] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
        commit: 18c75784e4a9db5ed8cf6818a29ec0ac15ea2c8b
[16/42] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
        commit: 2d948e428c77b8764fe96537c70e5500b29f9c4e
[17/42] clk: qcom: gcc-sa8775p: Tie the CX power domain to controller
        commit: eed0a644a28a39d9da91a10d51b8f3247302a533
[18/42] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller
        commit: 40537977a0ff9a6a1bcc489863e5656914b1ac53
[19/42] clk: qcom: gcc-sc7280: Tie the CX power domain to controller
        commit: 503de100eb2823519b82d759ead69ee377289a9e
[20/42] clk: qcom: gcc-sdx75: Tie the CX power domain to controller
        commit: 563b9aceb53ea15f2ada9417809d1d9e9a2c1fd1
[21/42] clk: qcom: gcc-sm4450: Tie the CX power domain to controller
        commit: 9965e30e827665e2fc9f0b3271733feaee809d48
[22/42] clk: qcom: gcc-sm8350: Tie the CX power domain to controller
        commit: 4572e9c0c4d48447d22a25037cbd2fbfda74a8c2
[23/42] clk: qcom: gcc-sm8450: Tie the CX power domain to controller
        commit: 6742c3ce04e5d52f718e4b562d0a1d817e1d76db
[24/42] clk: qcom: gcc-sm8550: Tie the CX power domain to controller
        commit: fe2a50974f4a0c78a68931f156d99e0479a4f00a
[25/42] clk: qcom: gcc-sm8650: Tie the CX power domain to controller
        commit: e4e6177235c6e0342357c48497d6b1a546c0ae57
[26/42] clk: qcom: gcc-sm8750: Tie the CX power domain to controller
        commit: f593d28a9193f1b5a96eb69bc5eb4dda2eaebebf
[27/42] clk: qcom: gcc-x1e80100: Tie the CX power domain to controller
        commit: 965dd2be7d35b2474251ee60d44addb257c9c85f

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: (subset) [PATCH v5 00/42] clk: qcom: Tie CX power domains to GCCs

[Rob Herring]

On Fri, Sep 25, 2026 at 11:43 AM Bjorn Andersson <andersson@kernel.org> wrote:
>
>
> On Thu, 24 Sep 2026 13:39:16 +0300, Abel Vesa wrote:
> > Tie the CX power domain to GCC clock controllers for SDM670,
> > SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
> > SM4450, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
> > X1E80100, Eliza, Kaanapali, and QCS615.
> >
> > Enable runtime PM for GCC providers without critical clocks, allowing CX to
> > power down when their consumers release clocks and GDSCs.
> >
> > [...]
>
> Applied, thanks!
>
> [01/42] dt-bindings: clock: qcom: gcc-sdm845: Require CX power domain
>         commit: 55388f587b3301dffdb30074d00f069d80d29341
> [02/42] dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain
>         commit: 80d35f528a46b5f1e9777ce83de48fd9efa7c422
> [03/42] dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain
>         commit: 98e936c9d46a25b4eceacf907fe5d87b3999040e
> [04/42] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain
>         commit: 534af057998b59a4813fd2eba524f2f523f356d6
> [05/42] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain
>         commit: 4de0860a340888fd2582681facbceda71b375617
> [06/42] dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain
>         commit: 779dd957c4c8a7d7d0fd8ac03caa27fe6db23514
> [07/42] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain
>         commit: 5a577a480dd3d764cc2f55a112efc92d59ad59ec
> [08/42] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain
>         commit: 76615e10462c425f926e50dce52e9d23bb2f9428
> [09/42] dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain
>         commit: f9c74b6ed57922b1fdb1ed6835665e06b5ba01a5
> [10/42] dt-bindings: clock: qcom: sm4450-gcc: Add CX power domain
>         commit: df3faa0e74e433304f9a6f33d3ac4d3376fcdc06
> [11/42] dt-bindings: clock: qcom: gcc-sm6350: Add CX power domain
>         commit: 3d4f3414300bba79d517585ac10181e285ca6be3
> [12/42] dt-bindings: clock: qcom: qcs8300-gcc: Add CX power domain
>         commit: fcf1810fede27777f9b708a9cef431bcac1d8e38
> [13/42] dt-bindings: clock: qcom: sdx75-gcc: Add CX power domain
>         commit: 6df1fd0bfa649c0f13abd026a01dbed5f1727fea
> [14/42] clk: qcom: gcc-eliza: Tie the CX power domain to controller
>         commit: 4eb8f2ad36888e5b29aa0a5e7e0bc60e382312ea
> [15/42] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
>         commit: 18c75784e4a9db5ed8cf6818a29ec0ac15ea2c8b
> [16/42] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
>         commit: 2d948e428c77b8764fe96537c70e5500b29f9c4e
> [17/42] clk: qcom: gcc-sa8775p: Tie the CX power domain to controller
>         commit: eed0a644a28a39d9da91a10d51b8f3247302a533
> [18/42] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller
>         commit: 40537977a0ff9a6a1bcc489863e5656914b1ac53
> [19/42] clk: qcom: gcc-sc7280: Tie the CX power domain to controller
>         commit: 503de100eb2823519b82d759ead69ee377289a9e
> [20/42] clk: qcom: gcc-sdx75: Tie the CX power domain to controller
>         commit: 563b9aceb53ea15f2ada9417809d1d9e9a2c1fd1
> [21/42] clk: qcom: gcc-sm4450: Tie the CX power domain to controller
>         commit: 9965e30e827665e2fc9f0b3271733feaee809d48
> [22/42] clk: qcom: gcc-sm8350: Tie the CX power domain to controller
>         commit: 4572e9c0c4d48447d22a25037cbd2fbfda74a8c2
> [23/42] clk: qcom: gcc-sm8450: Tie the CX power domain to controller
>         commit: 6742c3ce04e5d52f718e4b562d0a1d817e1d76db
> [24/42] clk: qcom: gcc-sm8550: Tie the CX power domain to controller
>         commit: fe2a50974f4a0c78a68931f156d99e0479a4f00a
> [25/42] clk: qcom: gcc-sm8650: Tie the CX power domain to controller
>         commit: e4e6177235c6e0342357c48497d6b1a546c0ae57
> [26/42] clk: qcom: gcc-sm8750: Tie the CX power domain to controller
>         commit: f593d28a9193f1b5a96eb69bc5eb4dda2eaebebf
> [27/42] clk: qcom: gcc-x1e80100: Tie the CX power domain to controller
>         commit: 965dd2be7d35b2474251ee60d44addb257c9c85f

Pretty sure this has introduced a bunch of warnings for qcom. Where's
the .dts changes?

We've really got to stop merging binding changes that introduce
warnings to existing .dts files.

     14 clock-controller@100000 (qcom,sm8550-gcc): 'power-domains' is
a required property
     12 syscon@9a10000 (syscon): compatible: ['syscon'] is too short
     11 clock-controller@100000 (qcom,gcc-sm8250): 'power-domains' is
a required property
      9 clock-controller@100000 (qcom,qcs8300-gcc): 'power-domains' is
a required property
      8 clock-controller@100000 (qcom,sm8650-gcc): 'power-domains' is
a required property
      8 clock-controller@100000 (qcom,qcs615-gcc): 'power-domains' is
a required property
      6 clock-controller@100000 (qcom,gcc-sm8150): 'power-domains' is
a required property
      5 clock-controller@100000 (qcom,gcc-sm8450): 'power-domains' is
a required property
      5 clock-controller@100000 (qcom,gcc-sm8350): 'power-domains' is
a required property
      2 clock-controller@100000 (qcom,sm8750-gcc): 'power-domains' is
a required property
      2 clock-controller@100000 (qcom,kaanapali-gcc): 'power-domains'
is a required property
      2 clock-controller@100000 (qcom,gcc-sm6350): 'power-domains' is
a required property
      2 clock-controller@100000 (qcom,gcc-sdm670): 'power-domains' is
a required property
      1 clock-controller@80000 (qcom,sdx75-gcc): 'power-domains' is a
required property
      1 clock-controller@100000 (qcom,sm4450-gcc): 'power-domains' is
a required property


Rob

Re: (subset) [PATCH v5 00/42] clk: qcom: Tie CX power domains to GCCs

[Bjorn Andersson]

On Tue, Sep 29, 2026 at 04:50:53PM -0500, Rob Herring wrote:
> On Fri, Sep 25, 2026 at 11:43 AM Bjorn Andersson <andersson@kernel.org> wrote:
> >
> >
> > On Thu, 24 Sep 2026 13:39:16 +0300, Abel Vesa wrote:
> > > Tie the CX power domain to GCC clock controllers for SDM670,
> > > SM8150, SM8250, SM8350, SM8450, SM8550, SM8650, SM8750, SM6350,
> > > SM4450, QCS8300, SDX75, SAR2130P, SC7180, SC7280, SA8775P,
> > > X1E80100, Eliza, Kaanapali, and QCS615.
> > >
> > > Enable runtime PM for GCC providers without critical clocks, allowing CX to
> > > power down when their consumers release clocks and GDSCs.
> > >
> > > [...]
> >
> > Applied, thanks!
> >
> > [01/42] dt-bindings: clock: qcom: gcc-sdm845: Require CX power domain
> >         commit: 55388f587b3301dffdb30074d00f069d80d29341
> > [02/42] dt-bindings: clock: qcom: gcc-sm8150: Add CX power domain
> >         commit: 80d35f528a46b5f1e9777ce83de48fd9efa7c422
> > [03/42] dt-bindings: clock: qcom: gcc-sm8250: Add CX power domain
> >         commit: 98e936c9d46a25b4eceacf907fe5d87b3999040e
> > [04/42] dt-bindings: clock: qcom: gcc-sm8350: Add CX power domain
> >         commit: 534af057998b59a4813fd2eba524f2f523f356d6
> > [05/42] dt-bindings: clock: qcom: gcc-sm8450: Add CX power domain
> >         commit: 4de0860a340888fd2582681facbceda71b375617
> > [06/42] dt-bindings: clock: qcom: qcs615-gcc: Add CX power domain
> >         commit: 779dd957c4c8a7d7d0fd8ac03caa27fe6db23514
> > [07/42] dt-bindings: clock: qcom: sm8550-gcc: Add CX power domain
> >         commit: 5a577a480dd3d764cc2f55a112efc92d59ad59ec
> > [08/42] dt-bindings: clock: qcom: sm8650-gcc: Add CX power domain
> >         commit: 76615e10462c425f926e50dce52e9d23bb2f9428
> > [09/42] dt-bindings: clock: qcom: sm8750-gcc: Add CX power domain
> >         commit: f9c74b6ed57922b1fdb1ed6835665e06b5ba01a5
> > [10/42] dt-bindings: clock: qcom: sm4450-gcc: Add CX power domain
> >         commit: df3faa0e74e433304f9a6f33d3ac4d3376fcdc06
> > [11/42] dt-bindings: clock: qcom: gcc-sm6350: Add CX power domain
> >         commit: 3d4f3414300bba79d517585ac10181e285ca6be3
> > [12/42] dt-bindings: clock: qcom: qcs8300-gcc: Add CX power domain
> >         commit: fcf1810fede27777f9b708a9cef431bcac1d8e38
> > [13/42] dt-bindings: clock: qcom: sdx75-gcc: Add CX power domain
> >         commit: 6df1fd0bfa649c0f13abd026a01dbed5f1727fea
> > [14/42] clk: qcom: gcc-eliza: Tie the CX power domain to controller
> >         commit: 4eb8f2ad36888e5b29aa0a5e7e0bc60e382312ea
> > [15/42] clk: qcom: gcc-kaanapali: Tie the CX power domain to controller
> >         commit: 18c75784e4a9db5ed8cf6818a29ec0ac15ea2c8b
> > [16/42] clk: qcom: gcc-qcs8300: Tie the CX power domain to controller
> >         commit: 2d948e428c77b8764fe96537c70e5500b29f9c4e
> > [17/42] clk: qcom: gcc-sa8775p: Tie the CX power domain to controller
> >         commit: eed0a644a28a39d9da91a10d51b8f3247302a533
> > [18/42] clk: qcom: gcc-sar2130p: Tie the CX power domain to controller
> >         commit: 40537977a0ff9a6a1bcc489863e5656914b1ac53
> > [19/42] clk: qcom: gcc-sc7280: Tie the CX power domain to controller
> >         commit: 503de100eb2823519b82d759ead69ee377289a9e
> > [20/42] clk: qcom: gcc-sdx75: Tie the CX power domain to controller
> >         commit: 563b9aceb53ea15f2ada9417809d1d9e9a2c1fd1
> > [21/42] clk: qcom: gcc-sm4450: Tie the CX power domain to controller
> >         commit: 9965e30e827665e2fc9f0b3271733feaee809d48
> > [22/42] clk: qcom: gcc-sm8350: Tie the CX power domain to controller
> >         commit: 4572e9c0c4d48447d22a25037cbd2fbfda74a8c2
> > [23/42] clk: qcom: gcc-sm8450: Tie the CX power domain to controller
> >         commit: 6742c3ce04e5d52f718e4b562d0a1d817e1d76db
> > [24/42] clk: qcom: gcc-sm8550: Tie the CX power domain to controller
> >         commit: fe2a50974f4a0c78a68931f156d99e0479a4f00a
> > [25/42] clk: qcom: gcc-sm8650: Tie the CX power domain to controller
> >         commit: e4e6177235c6e0342357c48497d6b1a546c0ae57
> > [26/42] clk: qcom: gcc-sm8750: Tie the CX power domain to controller
> >         commit: f593d28a9193f1b5a96eb69bc5eb4dda2eaebebf
> > [27/42] clk: qcom: gcc-x1e80100: Tie the CX power domain to controller
> >         commit: 965dd2be7d35b2474251ee60d44addb257c9c85f
> 
> Pretty sure this has introduced a bunch of warnings for qcom. Where's
> the .dts changes?
> 

My bad. I test every dts change against the current bindings in
linux-next, but not the other way around - so I failed to spot the
introduced warnings.

> We've really got to stop merging binding changes that introduce
> warnings to existing .dts files.
> 

Warnings we can fix, the possible regressions in backwards compatibility
is a bigger concern to me. So that's another pass I need to figure out
how to incorporate in my workflow.

Regards,
Bjorn

>      14 clock-controller@100000 (qcom,sm8550-gcc): 'power-domains' is
> a required property
>      12 syscon@9a10000 (syscon): compatible: ['syscon'] is too short
>      11 clock-controller@100000 (qcom,gcc-sm8250): 'power-domains' is
> a required property
>       9 clock-controller@100000 (qcom,qcs8300-gcc): 'power-domains' is
> a required property
>       8 clock-controller@100000 (qcom,sm8650-gcc): 'power-domains' is
> a required property
>       8 clock-controller@100000 (qcom,qcs615-gcc): 'power-domains' is
> a required property
>       6 clock-controller@100000 (qcom,gcc-sm8150): 'power-domains' is
> a required property
>       5 clock-controller@100000 (qcom,gcc-sm8450): 'power-domains' is
> a required property
>       5 clock-controller@100000 (qcom,gcc-sm8350): 'power-domains' is
> a required property
>       2 clock-controller@100000 (qcom,sm8750-gcc): 'power-domains' is
> a required property
>       2 clock-controller@100000 (qcom,kaanapali-gcc): 'power-domains'
> is a required property
>       2 clock-controller@100000 (qcom,gcc-sm6350): 'power-domains' is
> a required property
>       2 clock-controller@100000 (qcom,gcc-sdm670): 'power-domains' is
> a required property
>       1 clock-controller@80000 (qcom,sdx75-gcc): 'power-domains' is a
> required property
>       1 clock-controller@100000 (qcom,sm4450-gcc): 'power-domains' is
> a required property
> 
> 
> Rob