From: Charles Keepax <ckeepax@opensource.cirrus.com>
To: HyeongJun An <sammiee5311@gmail.com>
Cc: lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz,
tiwai@suse.com, linux-sound@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ASoC: wm8903: Move the DRC QR threshold to the register that holds it
Date: Mon, 21 Sep 2026 10:19:08 +0100 [thread overview]
Message-ID: <arD2jB5Q+fJ3u1DW@opensource.cirrus.com> (raw)
In-Reply-To: <20260920135327.3628704-1-sammiee5311@gmail.com>
On Sun, Sep 20, 2026 at 10:53:27PM +0900, HyeongJun An wrote:
> The DRC_THRESH_QR field is bits 7 and 6 of DRC_1, but the control sits on
> DRC_0. Its shift and max are right for the field, only the register is
> wrong.
>
> Those bits of DRC_0 belong to DRC_STARTUP_GAIN, which "DRC Startup
> Volume" claims as bits 10 to 6. So the two controls share bits 7 and 6.
> Writing either one moves the other, and the quick release threshold is
> never reached at all.
>
> The six fields of DRC_1 tile it exactly, so there is nowhere else the
> threshold could live. Point the control at DRC_1.
>
> Found by a sweep for two controls claiming the same bits of one
> register. No board with this codec was to hand, the register map is
> the driver's own wm8903.h.
>
> Fixes: f1c0a02f32f8 ("ALSA: ASoC: Add WM8903 CODEC driver")
> Signed-off-by: HyeongJun An <sammiee5311@gmail.com>
> Assisted-by: Claude:claude-opus-5
> ---
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Thanks,
Charles
next prev parent reply other threads:[~2026-09-21 9:19 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-20 13:53 HyeongJun An
2026-09-21 9:19 ` Charles Keepax [this message]
2026-09-21 10:13 ` Mark Brown
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