[PATCH] ASoC: wm8903: Move the DRC QR threshold to the register that holds it

[PATCH] ASoC: wm8903: Move the DRC QR threshold to the register that holds it

[HyeongJun An]

The DRC_THRESH_QR field is bits 7 and 6 of DRC_1, but the control sits on
DRC_0. Its shift and max are right for the field, only the register is
wrong.

Those bits of DRC_0 belong to DRC_STARTUP_GAIN, which "DRC Startup
Volume" claims as bits 10 to 6. So the two controls share bits 7 and 6.
Writing either one moves the other, and the quick release threshold is
never reached at all.

The six fields of DRC_1 tile it exactly, so there is nowhere else the
threshold could live. Point the control at DRC_1.

Found by a sweep for two controls claiming the same bits of one
register. No board with this codec was to hand, the register map is
the driver's own wm8903.h.

Fixes: f1c0a02f32f8 ("ALSA: ASoC: Add WM8903 CODEC driver")
Signed-off-by: HyeongJun An <sammiee5311@gmail.com>
Assisted-by: Claude:claude-opus-5
---
 sound/soc/codecs/wm8903.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index 156e1e24a388..fbf388cf966d 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -676,7 +676,7 @@ SOC_ENUM("DRC Decay Rate", drc_decay),
 SOC_ENUM("DRC FF Delay", drc_ff_delay),
 SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
 SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
-SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
+SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_1, 6, 3, 0, drc_tlv_max),
 SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
 SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
 SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
-- 
2.43.0

Re: [PATCH] ASoC: wm8903: Move the DRC QR threshold to the register that holds it

[Charles Keepax]

On Sun, Sep 20, 2026 at 10:53:27PM +0900, HyeongJun An wrote:
> The DRC_THRESH_QR field is bits 7 and 6 of DRC_1, but the control sits on
> DRC_0. Its shift and max are right for the field, only the register is
> wrong.
> 
> Those bits of DRC_0 belong to DRC_STARTUP_GAIN, which "DRC Startup
> Volume" claims as bits 10 to 6. So the two controls share bits 7 and 6.
> Writing either one moves the other, and the quick release threshold is
> never reached at all.
> 
> The six fields of DRC_1 tile it exactly, so there is nowhere else the
> threshold could live. Point the control at DRC_1.
> 
> Found by a sweep for two controls claiming the same bits of one
> register. No board with this codec was to hand, the register map is
> the driver's own wm8903.h.
> 
> Fixes: f1c0a02f32f8 ("ALSA: ASoC: Add WM8903 CODEC driver")
> Signed-off-by: HyeongJun An <sammiee5311@gmail.com>
> Assisted-by: Claude:claude-opus-5
> ---

Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>

Thanks,
Charles

Re: [PATCH] ASoC: wm8903: Move the DRC QR threshold to the register that holds it

[Mark Brown]

On Sun, 20 Sep 2026 22:53:27 +0900, HyeongJun An wrote:
> ASoC: wm8903: Move the DRC QR threshold to the register that holds it

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.3

Thanks!

[1/1] ASoC: wm8903: Move the DRC QR threshold to the register that holds it
      https://git.kernel.org/broonie/sound/c/e31ae4aeb049

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark