[PATCH v2 0/3] soc/tegra: fuse: Add Tegra264 support

[PATCH v2 0/3] soc/tegra: fuse: Add Tegra264 support

[Jon Hunter]

This series adds support for the FUSE block found on Tegra264. The first
two patches were originally posted by Thierry Reding and add the device
tree binding and FUSE node. The third patch adds the Tegra264 FUSE SoC
data, including the register range and keepouts.

Changes in v2:
- Reword the device tree binding commit message following review
  feedback
- Correct the register range for the efuse block to map the complete
  address space.
- Add Tegra264 FUSE driver support

Link: https://lore.kernel.org/linux-tegra/20260320233822.2578569-1-thierry.reding@kernel.org/
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
Jon Hunter (1):
      soc/tegra: fuse: Add Tegra264 support

Thierry Reding (2):
      dt-bindings: fuse: Document compatible string for Tegra264 FUSE
      arm64: tegra: Add FUSE block on Tegra264

 .../bindings/fuse/nvidia,tegra20-fuse.yaml         |   1 +
 arch/arm64/boot/dts/nvidia/tegra264.dtsi           |   7 +
 drivers/soc/tegra/fuse/fuse-tegra.c                |  11 +-
 drivers/soc/tegra/fuse/fuse-tegra30.c              | 168 ++++++++++++++++++++-
 drivers/soc/tegra/fuse/fuse.h                      |   7 +-
 5 files changed, 191 insertions(+), 3 deletions(-)
---
base-commit: e6e35979777d646fe3c7c94dca7dd32fb25d45f4
change-id: 20260916-tegra-tegra264-fuse-5561d592539d

Best regards,
-- 
Jon Hunter <jonathanh@nvidia.com>

[PATCH v2 1/3] dt-bindings: fuse: Document compatible string for Tegra264 FUSE

[Jon Hunter]

From: Thierry Reding <treding@nvidia.com>

Add the compatible string for the fuse device on Tegra264. This hardware
block is mostly the same as the one found on earlier generations,
however, the exact register regions that can be accessed differ.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
index 02f0b04623776d2fa60d71c442722d37be015910..bf9923b638527984d27c99b90972487bae05b202 100644
--- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
+++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml
@@ -22,6 +22,7 @@ properties:
           - nvidia,tegra186-efuse
           - nvidia,tegra194-efuse
           - nvidia,tegra234-efuse
+          - nvidia,tegra264-efuse
 
       - items:
           - const: nvidia,tegra132-efuse

-- 
2.43.0

[PATCH v2 2/3] arm64: tegra: Add FUSE block on Tegra264

[Jon Hunter]

From: Thierry Reding <treding@nvidia.com>

The FUSE block contains a number of registers exposing information that
is useful for certain drivers and/or userspace to read at runtime.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index b84f93ad227e624a696f50c4e86c7909901096bd..dd81ce3b36aee163d81437d0a7fed0ccde2748d8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -43,6 +43,13 @@ misc@100000 {
 			      <0x0 0x0c140000 0x0 0x10000>;
 		};
 
+		fuse@1000000 {
+			compatible = "nvidia,tegra264-efuse";
+			reg = <0x0 0x1000000 0x0 0x20000>;
+			clocks = <&bpmp TEGRA264_CLK_FUSE>;
+			clock-names = "fuse";
+		};
+
 		timer@8000000 {
 			compatible = "nvidia,tegra234-timer";
 			reg = <0x0 0x08000000 0x0 0x140000>;

-- 
2.43.0

[PATCH v2 3/3] soc/tegra: fuse: Add Tegra264 support

[Jon Hunter]

Add the fuse SoC data for the Tegra264 device which defines the address
range and keepouts for the fuse registers.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c   |  11 ++-
 drivers/soc/tegra/fuse/fuse-tegra30.c | 168 +++++++++++++++++++++++++++++++++-
 drivers/soc/tegra/fuse/fuse.h         |   7 +-
 3 files changed, 183 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index 39654964c35c3e59e142f74b09fc60cb3515c78a..b8c8ccf80056cbf13318f7ad06de6c658f52ad41 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -65,6 +65,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) {
 };
 
 static const struct of_device_id tegra_fuse_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_264_SOC
+	{ .compatible = "nvidia,tegra264-efuse", .data = &tegra264_fuse_soc },
+#endif
 #ifdef CONFIG_ARCH_TEGRA_234_SOC
 	{ .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
 #endif
@@ -175,6 +178,11 @@ static int tegra_fuse_probe(struct platform_device *pdev)
 		case TEGRA241:
 			fuse->soc = &tegra241_fuse_soc;
 			break;
+#endif
+#if defined(CONFIG_ARCH_TEGRA_264_SOC)
+		case TEGRA264:
+			fuse->soc = &tegra264_fuse_soc;
+			break;
 #endif
 		default:
 			return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip);
@@ -413,7 +421,8 @@ const struct attribute_group tegra_soc_attr_group = {
 
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
-    IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
+    IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
 			     char *buf)
 {
diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c
index 2fad8b13a3b9615b46187ecfc6f975dd8e0f6e80..623848116b693b2a4c6669538f096b99943f420a 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra30.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra30.c
@@ -39,7 +39,8 @@
     defined(CONFIG_ARCH_TEGRA_186_SOC) || \
     defined(CONFIG_ARCH_TEGRA_194_SOC) || \
     defined(CONFIG_ARCH_TEGRA_234_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_241_SOC)
+    defined(CONFIG_ARCH_TEGRA_241_SOC) || \
+    defined(CONFIG_ARCH_TEGRA_264_SOC)
 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
 {
 	if (WARN_ON(!fuse->base))
@@ -802,3 +803,168 @@ const struct tegra_fuse_soc tegra241_fuse_soc = {
 	.soc_attr_group = &tegra194_soc_attr_group,
 };
 #endif
+
+#ifdef CONFIG_ARCH_TEGRA_264_SOC
+static const struct nvmem_keepout tegra264_fuse_keepouts[] = {
+	{ .start = 0x0019c, .end = 0x001a0 },
+	{ .start = 0x00308, .end = 0x00310 },
+	{ .start = 0x0032c, .end = 0x00334 },
+	{ .start = 0x00350, .end = 0x00354 },
+	{ .start = 0x00494, .end = 0x0049c },
+	{ .start = 0x0078c, .end = 0x00790 },
+	{ .start = 0x007a0, .end = 0x007a8 },
+	{ .start = 0x007dc, .end = 0x007e4 },
+	{ .start = 0x008d8, .end = 0x008dc },
+	{ .start = 0x0096c, .end = 0x00970 },
+	{ .start = 0x00974, .end = 0x0097c },
+	{ .start = 0x009f4, .end = 0x009f8 },
+	{ .start = 0x00a14, .end = 0x00a20 },
+	{ .start = 0x00a44, .end = 0x00a4c },
+	{ .start = 0x00a50, .end = 0x00a58 },
+	{ .start = 0x00a5c, .end = 0x00a64 },
+	{ .start = 0x00a68, .end = 0x00a70 },
+	{ .start = 0x00acc, .end = 0x00ad0 },
+	{ .start = 0x00b0c, .end = 0x00b18 },
+	{ .start = 0x00c80, .end = 0x00c8c },
+	{ .start = 0x00dac, .end = 0x00db4 },
+	{ .start = 0x00db8, .end = 0x00dbc },
+	{ .start = 0x00e0c, .end = 0x00e10 },
+	{ .start = 0x00fd0, .end = 0x01f00 },
+	{ .start = 0x01f1c, .end = 0x10064 },
+	{ .start = 0x10084, .end = 0x100a0 },
+	{ .start = 0x100a4, .end = 0x1019c },
+	{ .start = 0x101a0, .end = 0x101cc },
+	{ .start = 0x101d0, .end = 0x10308 },
+	{ .start = 0x10310, .end = 0x1055c },
+	{ .start = 0x1057c, .end = 0x106b0 },
+	{ .start = 0x106b4, .end = 0x11008 },
+	{ .start = 0x1100c, .end = 0x11018 },
+	{ .start = 0x11020, .end = 0x110b8 },
+	{ .start = 0x110c4, .end = 0x110c8 },
+	{ .start = 0x110e8, .end = 0x110ec },
+	{ .start = 0x110f0, .end = 0x11124 },
+	{ .start = 0x11128, .end = 0x11168 },
+	{ .start = 0x1116c, .end = 0x111b8 },
+	{ .start = 0x111bc, .end = 0x111e4 },
+	{ .start = 0x111e8, .end = 0x111ec },
+	{ .start = 0x111f0, .end = 0x1121c },
+	{ .start = 0x11250, .end = 0x1133c },
+	{ .start = 0x11340, .end = 0x113c8 },
+	{ .start = 0x113d0, .end = 0x11420 },
+	{ .start = 0x11430, .end = 0x11440 },
+	{ .start = 0x11444, .end = 0x11468 },
+	{ .start = 0x1146c, .end = 0x114a8 },
+	{ .start = 0x114ac, .end = 0x115cc },
+	{ .start = 0x115d0, .end = 0x115dc },
+	{ .start = 0x115e0, .end = 0x116b4 },
+	{ .start = 0x116bc, .end = 0x11740 },
+	{ .start = 0x11744, .end = 0x117b8 },
+	{ .start = 0x117bc, .end = 0x11810 },
+	{ .start = 0x11814, .end = 0x11850 },
+	{ .start = 0x11858, .end = 0x118a0 },
+	{ .start = 0x118ac, .end = 0x11b48 },
+	{ .start = 0x11b50, .end = 0x11b5c },
+	{ .start = 0x11b60, .end = 0x11bf8 },
+	{ .start = 0x11bfc, .end = 0x11c18 },
+	{ .start = 0x11c40, .end = 0x12000 },
+	{ .start = 0x12004, .end = 0x12010 },
+	{ .start = 0x12014, .end = 0x120fc },
+	{ .start = 0x1211c, .end = 0x12120 },
+	{ .start = 0x12124, .end = 0x12144 },
+	{ .start = 0x1214c, .end = 0x12300 },
+	{ .start = 0x12308, .end = 0x1236c },
+	{ .start = 0x12370, .end = 0x126ac },
+	{ .start = 0x126b0, .end = 0x12c60 },
+	{ .start = 0x12c64, .end = 0x12d94 },
+	{ .start = 0x12da4, .end = 0x13004 },
+	{ .start = 0x13008, .end = 0x1300c },
+	{ .start = 0x13010, .end = 0x13014 },
+	{ .start = 0x13018, .end = 0x13020 },
+	{ .start = 0x13064, .end = 0x13084 },
+	{ .start = 0x130a0, .end = 0x130a4 },
+	{ .start = 0x130b8, .end = 0x130c4 },
+	{ .start = 0x130c8, .end = 0x130e8 },
+	{ .start = 0x130ec, .end = 0x130f0 },
+	{ .start = 0x130fc, .end = 0x1311c },
+	{ .start = 0x13120, .end = 0x13128 },
+	{ .start = 0x13144, .end = 0x1314c },
+	{ .start = 0x13168, .end = 0x1316c },
+	{ .start = 0x1319c, .end = 0x131a0 },
+	{ .start = 0x131ac, .end = 0x131c0 },
+	{ .start = 0x131cc, .end = 0x131d0 },
+	{ .start = 0x131e4, .end = 0x131e8 },
+	{ .start = 0x131ec, .end = 0x131f0 },
+	{ .start = 0x1321c, .end = 0x13250 },
+	{ .start = 0x132f0, .end = 0x13310 },
+	{ .start = 0x1332c, .end = 0x13334 },
+	{ .start = 0x1333c, .end = 0x13344 },
+	{ .start = 0x13350, .end = 0x13354 },
+	{ .start = 0x1336c, .end = 0x13370 },
+	{ .start = 0x133ac, .end = 0x133b0 },
+	{ .start = 0x133c8, .end = 0x133d0 },
+	{ .start = 0x13420, .end = 0x13430 },
+	{ .start = 0x13440, .end = 0x13444 },
+	{ .start = 0x13468, .end = 0x13470 },
+	{ .start = 0x13494, .end = 0x1349c },
+	{ .start = 0x134a8, .end = 0x134ac },
+	{ .start = 0x13544, .end = 0x1354c },
+	{ .start = 0x1355c, .end = 0x1357c },
+	{ .start = 0x135cc, .end = 0x135e0 },
+	{ .start = 0x135e4, .end = 0x13608 },
+	{ .start = 0x1360c, .end = 0x13620 },
+	{ .start = 0x136ac, .end = 0x136bc },
+	{ .start = 0x136c0, .end = 0x136c8 },
+	{ .start = 0x13714, .end = 0x13718 },
+	{ .start = 0x13724, .end = 0x13728 },
+	{ .start = 0x1372c, .end = 0x13730 },
+	{ .start = 0x13734, .end = 0x1373c },
+	{ .start = 0x13740, .end = 0x13744 },
+	{ .start = 0x13754, .end = 0x13758 },
+	{ .start = 0x13760, .end = 0x13784 },
+	{ .start = 0x1378c, .end = 0x13790 },
+	{ .start = 0x137a0, .end = 0x137a8 },
+	{ .start = 0x137b8, .end = 0x137bc },
+	{ .start = 0x137dc, .end = 0x137e4 },
+	{ .start = 0x137ec, .end = 0x137f0 },
+	{ .start = 0x13800, .end = 0x13818 },
+	{ .start = 0x13820, .end = 0x13828 },
+	{ .start = 0x13830, .end = 0x13858 },
+	{ .start = 0x138a0, .end = 0x138b0 },
+	{ .start = 0x138d0, .end = 0x138dc },
+	{ .start = 0x1396c, .end = 0x13970 },
+	{ .start = 0x13974, .end = 0x1397c },
+	{ .start = 0x139f4, .end = 0x139f8 },
+	{ .start = 0x13a14, .end = 0x13a20 },
+	{ .start = 0x13a44, .end = 0x13a4c },
+	{ .start = 0x13a50, .end = 0x13a58 },
+	{ .start = 0x13a5c, .end = 0x13a64 },
+	{ .start = 0x13a68, .end = 0x13a70 },
+	{ .start = 0x13acc, .end = 0x13ad8 },
+	{ .start = 0x13b0c, .end = 0x13b18 },
+	{ .start = 0x13b48, .end = 0x13b50 },
+	{ .start = 0x13b5c, .end = 0x13b60 },
+	{ .start = 0x13bf8, .end = 0x13bfc },
+	{ .start = 0x13c18, .end = 0x13c40 },
+	{ .start = 0x13c60, .end = 0x13c64 },
+	{ .start = 0x13c74, .end = 0x13c8c },
+	{ .start = 0x13d94, .end = 0x13da4 },
+	{ .start = 0x13dac, .end = 0x13db4 },
+	{ .start = 0x13db8, .end = 0x13dbc },
+	{ .start = 0x13df4, .end = 0x13e04 },
+	{ .start = 0x13e0c, .end = 0x13e10 },
+};
+
+static const struct tegra_fuse_info tegra264_fuse_info = {
+	.read = tegra30_fuse_read,
+	.size = 0x13eb8,
+};
+
+const struct tegra_fuse_soc tegra264_fuse_soc = {
+	.init = tegra30_fuse_init,
+	.info = &tegra264_fuse_info,
+	.keepouts = tegra264_fuse_keepouts,
+	.num_keepouts = ARRAY_SIZE(tegra264_fuse_keepouts),
+	.soc_attr_group = &tegra194_soc_attr_group,
+	.clk_suspend_on = false,
+};
+#endif
diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h
index 9fee6ad6ad9e98852c9d47079cdf49433e55fdb7..0fb97508db0a56c742cca6f7d1175b714aa7099c 100644
--- a/drivers/soc/tegra/fuse/fuse.h
+++ b/drivers/soc/tegra/fuse/fuse.h
@@ -125,7 +125,8 @@ extern const struct tegra_fuse_soc tegra186_fuse_soc;
 
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
-    IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
+    IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
 extern const struct attribute_group tegra194_soc_attr_group;
 #endif
 
@@ -141,4 +142,8 @@ extern const struct tegra_fuse_soc tegra234_fuse_soc;
 extern const struct tegra_fuse_soc tegra241_fuse_soc;
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_264_SOC
+extern const struct tegra_fuse_soc tegra264_fuse_soc;
+#endif
+
 #endif

-- 
2.43.0

Re: [PATCH v2 1/3] dt-bindings: fuse: Document compatible string for Tegra264 FUSE

[Krzysztof Kozlowski]

On Thu, Sep 17, 2026 at 10:16:01AM +0100, Jon Hunter wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Add the compatible string for the fuse device on Tegra264. This hardware
> block is mostly the same as the one found on earlier generations,
> however, the exact register regions that can be accessed differ.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 0/3] soc/tegra: fuse: Add Tegra264 support

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1393 bytes --]

On Thu, Sep 17, 2026 at 10:16:00AM +0100, Jon Hunter wrote:
> This series adds support for the FUSE block found on Tegra264. The first
> two patches were originally posted by Thierry Reding and add the device
> tree binding and FUSE node. The third patch adds the Tegra264 FUSE SoC
> data, including the register range and keepouts.
> 
> Changes in v2:
> - Reword the device tree binding commit message following review
>   feedback
> - Correct the register range for the efuse block to map the complete
>   address space.
> - Add Tegra264 FUSE driver support
> 
> Link: https://lore.kernel.org/linux-tegra/20260320233822.2578569-1-thierry.reding@kernel.org/
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> Jon Hunter (1):
>       soc/tegra: fuse: Add Tegra264 support
> 
> Thierry Reding (2):
>       dt-bindings: fuse: Document compatible string for Tegra264 FUSE
>       arm64: tegra: Add FUSE block on Tegra264
> 
>  .../bindings/fuse/nvidia,tegra20-fuse.yaml         |   1 +
>  arch/arm64/boot/dts/nvidia/tegra264.dtsi           |   7 +
>  drivers/soc/tegra/fuse/fuse-tegra.c                |  11 +-
>  drivers/soc/tegra/fuse/fuse-tegra30.c              | 168 ++++++++++++++++++++-
>  drivers/soc/tegra/fuse/fuse.h                      |   7 +-
>  5 files changed, 191 insertions(+), 3 deletions(-)

All there patches applied, thanks.

Thierry

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