[PATCH v1 0/8] ASoC: qcom: Add audio support for Hawi and Maili platforms

[PATCH v1 0/8] ASoC: qcom: Add audio support for Hawi and Maili platforms

[Prasad Kumpatla]

This series enables the LPASS audio subsystem on the Qualcomm Hawi and
Maili platforms, wiring up playback and capture on their respective MTP
reference boards.

It adds the Maili sound card configuration and Maili LPASS macro codec
bindings, a WSA885x speaker-amplifier fix for back-to-back playback, the
device tree audio nodes for both SoCs and their MTP boards, and the
defconfig change to build the Hawi LPASS LPI pinctrl driver.

  ASoC: codecs: wsa885x: Reset registers on teardown for B2B playback
    Reset the I2S/TDM, clock-source and bandgap override registers in
    hw_free() so the amplifier comes up reliably on back-to-back streams.

  ASoC: qcom: sc8280xp: add Maili sound card configuration
    Add maili_priv_data with driver_name "maili" so the topology is
    loaded from the maili/ firmware directory.

  ASoC: dt-bindings: qcom: Add Maili LPASS macro codecs
    Document the LPASS macro codec compatibles for Maili.

  arm64: dts: qcom: hawi{,-mtp}: add the LPASS/codec device nodes for
    Hawi and enable the audio playback and capture paths on the Hawi MTP.

  arm64: dts: qcom: maili{,-mtp}: add the LPASS/codec device nodes for
    Maili and enable the audio playback and capture paths on the Maili MTP.

  arm64: defconfig: Enable Hawi LPASS LPI pinctrl driver
    Build CONFIG_PINCTRL_HAWI_LPASS_LPI as a module, required by both
    Hawi and Maili to control the LPI GPIOs.

This series depends on the following patches:

  [1] ASoC: qcom: Add QAIF AIF MI2S and TDM DAI support (Reviewed-by)
      https://lore.kernel.org/all/20260918-qaif_dai_id_support-v1-0-ed863c0e5e45@oss.qualcomm.com/

  [2] Add LPASS VA CSR HeartBeat pulse clock support (Reviewed-by)
      https://lore.kernel.org/all/20260917-master-v8-0-823d2c5d090a@oss.qualcomm.com/

  [3] ASoC: qcom: Add shikra and Hawi LPASS macro support (under review)
      https://lore.kernel.org/all/20260922-add_shikra_support-v1-0-6c6cb6444caf@oss.qualcomm.com/

  [4] arm64: dts: qcom: Introduce the Device Tree for the Hawi SoC (under review)
      https://lore.kernel.org/all/20260923-hawi-dt-post-v1-0-e41473b6298b@oss.qualcomm.com/

  [5] arm64: dts: qcom: Introduce the Device Tree for the Maili SoC (under review)
      https://lore.kernel.org/all/20260922-maili-dts-v1-0-ac2b1b76bfd9@oss.qualcomm.com/

Prasad Kumpatla (8):
  ASoC: codecs: wsa885x: Reset registers on teardown for B2B playback
  ASoC: qcom: sc8280xp: add Maili sound card configuration
  ASoC: dt-bindings: qcom: Add Maili LPASS macro codecs
  arm64: dts: qcom: hawi: add LPASS audio subsystem nodes
  arm64: dts: qcom: hawi-mtp: enable audio playback and capture
  arm64: dts: qcom: maili: add LPASS audio subsystem nodes
  arm64: dts: qcom: maili-mtp: enable audio playback and capture
  arm64: defconfig: Enable Hawi LPASS LPI pinctrl driver

 .../bindings/sound/qcom,lpass-rx-macro.yaml   |   3 +
 .../bindings/sound/qcom,lpass-tx-macro.yaml   |   3 +
 .../bindings/sound/qcom,lpass-va-macro.yaml   |   3 +
 arch/arm64/boot/dts/qcom/hawi-mtp.dts         | 206 +++++++++++++
 arch/arm64/boot/dts/qcom/hawi.dtsi            | 291 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/maili-mtp.dts        | 206 +++++++++++++
 arch/arm64/boot/dts/qcom/maili.dtsi           | 291 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |   1 +
 sound/soc/codecs/wsa885x.c                    |  11 +-
 sound/soc/qcom/sc8280xp.c                     |  11 +-
 10 files changed, 1024 insertions(+), 2 deletions(-)


base-commit: 6c58e38b255a3e0c11e513e3b8de85eb26fb02b5
prerequisite-patch-id: e6735f29343dd80d0e7ad48b6874eab4a5d7efc6
prerequisite-patch-id: ac7bc5ad958bb392a57871dde1f79c2fc520d482
prerequisite-patch-id: 332b888996b9d6c58e8c90eada37dc14137755ea
prerequisite-patch-id: 21e9dfd02f282ea4239f12d91ac8a2be76aaad29
prerequisite-patch-id: 52f17e16e09853e366ecc3da2676654df79daf06
prerequisite-patch-id: f0b1cd1f1f8daf0e1814a338446d493d64c9469f
prerequisite-patch-id: 29a1620a2ea61c0b7b052220e5ea522b1fbf2ad8
prerequisite-patch-id: 0872295385e6712bf342d84f095ec3710abde8d8
prerequisite-patch-id: 69807d41bbbd6177da4374639ae280501f3f60df
prerequisite-patch-id: d9f8613cac873926d6d2fd77e45002d34954b434
prerequisite-patch-id: 446fe28b27dbf5ce4240704d89296a5af69e8b21
prerequisite-patch-id: dc5ac9645789f25b3742dc4fca08dab4c1e4826d
prerequisite-patch-id: 0521512205679cad2462ecda959239aadc48cce6
-- 
2.34.1

[PATCH v1 1/8] ASoC: codecs: wsa885x: Reset registers on teardown for B2B playback

[Prasad Kumpatla]

During back-to-back speaker playback the PA sometimes fails to enable
because a few I2S/TDM and clock source registers retain their previous
state and are not reprogrammed on the next stream.

Reset the relevant I2S/TDM, clock source and bandgap override registers
in hw_free() so the codec is torn down cleanly and the speaker amplifier
comes up reliably on back-to-back use cases. Move the bandgap override
reset out of set_sysclk() into the teardown path where it belongs.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 sound/soc/codecs/wsa885x.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/sound/soc/codecs/wsa885x.c b/sound/soc/codecs/wsa885x.c
index 1faa8541a872..5ffbf9e89fd9 100644
--- a/sound/soc/codecs/wsa885x.c
+++ b/sound/soc/codecs/wsa885x.c
@@ -896,7 +896,6 @@ static int wsa885x_codec_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 
 	regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_SYS_CLK_SEL, 0x00);
 	regmap_write(wsa885x->regmap, WSA885X_DIG_CTRL0_POWER_FSM_CTL1, 0x01);
-	regmap_write(wsa885x->regmap, WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x00);
 
 	return 0;
 }
@@ -1006,6 +1005,16 @@ static int wsa885x_codec_hw_free(struct snd_pcm_substream *substream,
 				 struct snd_soc_dai *dai)
 {
 	static const struct reg_sequence regs[] = {
+		{ WSA885X_DIG_CTRL1_I2S_RESET_CTL, 0x00 },
+		{ WSA885X_DIG_CTRL1_I2S_CFG0_TDM_TX, 0x00 },
+		{ WSA885X_DIG_CTRL1_I2S_CFG1_TDM_TX, 0x00 },
+		{ WSA885X_DIG_CTRL1_I2S_TDM_CTL1, 0x05 },
+		{ WSA885X_DIG_CTRL1_I2S_TDM_CTL0, 0x00 },
+		{ WSA885X_DIG_CTRL1_I2S_TDM_CH_TX, 0x00 },
+		{ WSA885X_DIG_CTRL1_I2S_CTL0, 0x06 },
+		{ WSA885X_DIG_CTRL1_I2S_TDM_CH_RX, 0x08 },
+		{ WSA885X_DIG_CTRL0_CLK_SOURCE_ENABLE, 0x00 },
+		{ WSA885X_ANA_TOP_BG_TVP_OVRD_CTL, 0x00 },
 		{ WSA885X_DIG_CTRL0_PA_FSM_CTL, 0x00 },
 	};
 	struct wsa885x_priv *wsa885x;
-- 
2.34.1

[PATCH v1 2/8] ASoC: qcom: sc8280xp: add Maili sound card configuration

[Prasad Kumpatla]

Maili ships its own firmware, so its topology file has to live in a
separate maili/ firmware directory. The topology load path is derived
from the sound card driver_name, so reusing the Hawi data would look
up the topology under hawi/ instead.

Add a dedicated maili_priv_data with driver_name "maili" for the
qcom,maili-sndcard compatible so the topology is loaded from the maili/
directory. It keeps the same DAPM widgets and enables codec sysclk,
MI2S BCLK and WCD jack detection for the Maili audio pipeline.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 sound/soc/qcom/sc8280xp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
index 0876b9be136d..fed4d36e5437 100644
--- a/sound/soc/qcom/sc8280xp.c
+++ b/sound/soc/qcom/sc8280xp.c
@@ -463,6 +463,15 @@ static const struct qcom_snd_soc_common kaanapali_priv_data = {
 	.wcd_jack = true,
 };
 
+static const struct qcom_snd_soc_common maili_priv_data = {
+	.driver_name = "maili",
+	.dapm_widgets = sc8280xp_dapm_widgets,
+	.num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets),
+	.codec_sysclk_set = true,
+	.mi2s_bclk_enable = true,
+	.wcd_jack = true,
+};
+
 static const struct qcom_snd_soc_common qcs9100_priv_data = {
 	.driver_name = "sa8775p",
 	.dapm_widgets = sc8280xp_dapm_widgets,
@@ -565,7 +574,7 @@ static const struct of_device_id snd_sc8280xp_dt_match[] = {
 	{ .compatible = "qcom,eliza-sndcard", .data = &eliza_priv_data },
 	{ .compatible = "qcom,hawi-sndcard", .data = &hawi_priv_data },
 	{ .compatible = "qcom,kaanapali-sndcard", .data = &kaanapali_priv_data },
-	{ .compatible = "qcom,maili-sndcard", .data = &hawi_priv_data },
+	{ .compatible = "qcom,maili-sndcard", .data = &maili_priv_data },
 	{ .compatible = "qcom,qcm6490-idp-sndcard", .data = &qcm6490_priv_data },
 	{ .compatible = "qcom,qcs615-sndcard", .data = &qcs615_priv_data },
 	{ .compatible = "qcom,qcs6490-rb3gen2-sndcard", .data = &qcs6490_priv_data },
-- 
2.34.1

[PATCH v1 3/8] ASoC: dt-bindings: qcom: Add Maili LPASS macro codecs

[Prasad Kumpatla]

Add compatibles for the RX, TX and VA macro codecs found in the Low
Power Audio SubSystem (LPASS) of the Qualcomm Maili SoC.

The Maili RX, TX and VA macros are identical to their Hawi counterparts,
so document them with the corresponding Hawi compatible as fallback.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 .../devicetree/bindings/sound/qcom,lpass-rx-macro.yaml         | 3 +++
 .../devicetree/bindings/sound/qcom,lpass-tx-macro.yaml         | 3 +++
 .../devicetree/bindings/sound/qcom,lpass-va-macro.yaml         | 3 +++
 3 files changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
index 6aa8ccd60c01..de65a3159380 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
@@ -29,6 +29,9 @@ properties:
               - qcom,sm8750-lpass-rx-macro
               - qcom,x1e80100-lpass-rx-macro
           - const: qcom,sm8550-lpass-rx-macro
+      - items:
+          - const: qcom,maili-lpass-rx-macro
+          - const: qcom,hawi-lpass-rx-macro
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
index 2df72450d36f..0838ed63cb22 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml
@@ -28,6 +28,9 @@ properties:
               - qcom,sm8750-lpass-tx-macro
               - qcom,x1e80100-lpass-tx-macro
           - const: qcom,sm8550-lpass-tx-macro
+      - items:
+          - const: qcom,maili-lpass-tx-macro
+          - const: qcom,hawi-lpass-tx-macro
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
index 7d56f9c36056..481b76504c6b 100644
--- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml
@@ -30,6 +30,9 @@ properties:
               - qcom,sm8750-lpass-va-macro
               - qcom,x1e80100-lpass-va-macro
           - const: qcom,sm8550-lpass-va-macro
+      - items:
+          - const: qcom,maili-lpass-va-macro
+          - const: qcom,hawi-lpass-va-macro
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH v1 4/8] arm64: dts: qcom: hawi: add LPASS audio subsystem nodes

[Prasad Kumpatla]

Add the Low Power Audio SubSystem (LPASS) device tree infrastructure
for Hawi to describe the ADSP-based audio pipeline.

Add the GPR (Generic Packet Router) node with q6apm and q6prm audio
services, LPASS RX, TX and VA macro codecs, SoundWire controllers,
VA CSR clock provider, and LPI TLMM pinctrl node required by the audio
subsystem.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi.dtsi | 291 +++++++++++++++++++++++++++++
 1 file changed, 291 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index c7ae8133b9cd..a0807cd66a00 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -22,6 +22,8 @@
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 #include "hawi-ipcc.h"
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -3841,6 +3843,295 @@ compute-cb@8 {
 						dma-coherent;
 					};
 				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x0c01 0x80>,
+								 <&apps_smmu 0x0c41 0x20>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
+		lpass_rxmacro: codec@72c0000 {
+			compatible = "qcom,hawi-lpass-rx-macro";
+			reg = <0x0 0x072c0000 0x0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk", "lpr", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr1: soundwire@72d0000 {
+			compatible = "qcom,soundwire-v3.1.0";
+			reg = <0x0 0x072d0000 0x0 0x10000>;
+			interrupts = <GIC_ESPI 219 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&lpass_rxmacro>;
+			clock-names = "iface";
+			label = "RX";
+
+			pinctrl-0 = <&rx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <1>;
+			qcom,dout-ports = <11>;
+			qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		lpass_txmacro: codec@72e0000 {
+			compatible = "qcom,hawi-lpass-tx-macro";
+			reg = <0x0 0x72e0000 0x0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk", "lpr", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr2: soundwire@7e90000 {
+			compatible = "qcom,soundwire-v3.1.0";
+			reg = <0x0 0x7e90000 0x0 0x10000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "core", "wakeup";
+			clocks = <&lpass_txmacro>;
+			clock-names = "iface";
+			label = "TX";
+
+			pinctrl-0 = <&tx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <4>;
+			qcom,dout-ports = <0>;
+			qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+			qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x00 0x01>;
+			qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+			qcom,ports-hstart = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-hstop = /bits/ 8 <0xff 0xff 0x0f 0xff>;
+			qcom,ports-word-length = /bits/ 8 <0xff 0x00 0x00 0xff>;
+			qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x01 0x00>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		lpass_vamacro: codec@7ec0000 {
+			compatible = "qcom,hawi-lpass-va-macro";
+			reg = <0x0 0x07ec0000 0x0 0x2000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_va_csr>;
+			clock-names = "mclk", "lpr", "dcodec", "heartbeatpulse";
+
+			#clock-cells = <0>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
+		lpass_va_csr: va-csr@7ee0000 {
+			compatible = "qcom,hawi-lpass-va-csr";
+			reg = <0x0 0x07ee0000 0x0 0xe000>;
+			clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "lpr", "audio";
+			#clock-cells = <0>;
+		};
+
+		lpass_tlmm: pinctrl@7f60000 {
+			compatible = "qcom,hawi-lpass-lpi-pinctrl";
+			reg = <0x0 0x07f60000 0x0 0x20000>;
+
+			clocks = <&q6prmcc LPASS_HW_LPR_VOTE
+					  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "lpr", "audio";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+			dmic01_default: dmic01-default-state {
+				clk-pins {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			dmic23_default: dmic23-default-state {
+				clk-pins {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_active: lpi-i2s1-active-state {
+				clk-pins {
+					pins = "gpio10";
+					function = "i2s1_clk";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				ws-pins {
+					pins = "gpio11";
+					function = "i2s1_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio15", "gpio16";
+					function = "i2s1_data";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			lpi_i2s1_sleep: lpi-i2s1-sleep-state {
+				clk-pins {
+					pins = "gpio10";
+					function = "i2s1_clk";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+
+				ws-pins {
+					pins = "gpio11";
+					function = "i2s1_ws";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+
+				data-pins {
+					pins = "gpio15", "gpio16";
+					function = "i2s1_data";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+			};
+
+			rx_swr_active: rx-swr-active-state {
+				clk-pins {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			tx_swr_active: tx-swr-active-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
 			};
 		};
 
-- 
2.34.1

[PATCH v1 5/8] arm64: dts: qcom: hawi-mtp: enable audio playback and capture

[Prasad Kumpatla]

Wire up the audio use cases on the Hawi MTP board on top of the LPASS
nodes added to the SoC dtsi.

Add the sound card (qcom,hawi-sndcard) with the TDM playback, WCD
playback/capture and VA DMIC capture DAI links and the associated audio
routing. Describe the WCD9395 codec, enable the RX and TX SoundWire
controllers with their WCD RX/TX satellite ports, and add the WSA8855
speaker amplifier on i2c3. Configure the VA macro DMIC supply and the
required TLMM pin states (WCD reset, WSA IRQ, WSA shutdown).

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/hawi-mtp.dts | 206 ++++++++++++++++++++++++++
 1 file changed, 206 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/hawi-mtp.dts b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
index b7346e20bf02..6da4c242dae4 100644
--- a/arch/arm64/boot/dts/qcom/hawi-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/hawi-mtp.dts
@@ -5,10 +5,12 @@
 
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 
 #include "hawi.dtsi"
 
@@ -127,6 +129,122 @@ pmic_glink_dp_out: endpoint {
 		};
 	};
 
+	hawi_sound: sound {
+		compatible = "qcom,hawi-sndcard", "qcom,sm8450-sndcard";
+		model = "HAWI-MTP";
+
+		audio-routing = "IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS1",
+				"VA DMIC1", "MIC BIAS1",
+				"VA DMIC2", "MIC BIAS3",
+				"VA DMIC3", "MIC BIAS3",
+				"TX SWR_INPUT", "ADC2_OUTPUT";
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&lpi_i2s1_active>;
+		pinctrl-1 = <&lpi_i2s1_sleep>;
+
+		va-dmic-dai-link {
+			link-name = "VA DMIC Capture";
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			codec {
+				sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			codec {
+				sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-playback-dai-link {
+			link-name = "WSA Playback";
+
+			codec {
+				sound-dai = <&wsa885x>;
+				dai-tdm-slot-num = <2>;
+				dai-tdm-slot-width = <32>;
+				dai-tdm-slot-rx-mask = <1 1>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai AIF_TDM_RX_1>;
+				dai-tdm-slot-num = <2>;
+				dai-tdm-slot-width = <32>;
+				dai-tdm-slot-rx-mask = <1 1>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	wcd939x: audio-codec {
+		compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
+							 500000 500000 500000 500000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+		vdd-px-supply = <&vreg_l3i_1p2>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+
+		#sound-dai-cells = <1>;
+	};
+
 	sdcard_vdd_3p0: sdcard-vdd-3p0 {
 		compatible = "regulator-fixed";
 
@@ -145,6 +263,70 @@ sdcard_vdd_3p0: sdcard-vdd-3p0 {
 	};
 };
 
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l10b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+
+&q6apmbedai {
+	dai@40 {
+		reg = <AIF_TDM_RX_1>;
+		clocks = <&q6prmcc LPASS_CLK_ID_QAIF_IF1_IBIT
+			  LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+		clock-names = "bclk";
+	};
+};
+
+&i2c3 {
+	status = "okay";
+
+	wsa885x: speaker@c {
+		compatible = "qcom,wsa8855";
+		reg = <0x0c>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <77 IRQ_TYPE_EDGE_FALLING>;
+
+		pinctrl-0 = <&wsa885x_spkr_sd_n &wsa885x_irq_gpio>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&pmh0110_f_e0_gpios 11 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l2g_1p8>;
+		vdd-io-supply = <&vreg_l1g_1p2>;
+
+		qcom,battery-config = "1s";
+
+		#sound-dai-cells = <0>;
+
+		status = "okay";
+	};
+};
+
+&swr1 {
+	status = "okay";
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010e00";
+		reg = <0 4>;
+
+		qcom,rx-port-mapping = <1 2 3 4 5 9>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010e00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <3 3 3 4>;
+	};
+};
+
 &apps_rsc {
 	regulators-0 {
 		compatible = "qcom,pmh0101-rpmh-regulators";
@@ -813,6 +995,16 @@ &pcie1_port0 {
 	reset-gpios = <&tlmm 220 GPIO_ACTIVE_LOW>;
 };
 
+&pmh0110_f_e0_gpios {
+	wsa885x_spkr_sd_n: wsa885x-spkr-sd-n-state {
+		pins = "gpio11";
+		function = "normal";
+		input-disable;
+		output-enable;
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmh0101_flash {
 	status = "okay";
 
@@ -937,6 +1129,20 @@ &tlmm {
 			       <119 2>, /* SoCCP */
 			       <144 2>; /* CXM UART */
 
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio161";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	wsa885x_irq_gpio: wsa885x-irq-state {
+		pins = "gpio77";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
 	key_vol_up_default: key-vol-up-default-state {
 		pins = "gpio101";
 		function = "gpio";
-- 
2.34.1

[PATCH v1 6/8] arm64: dts: qcom: maili: add LPASS audio subsystem nodes

[Prasad Kumpatla]

Add the Low Power Audio SubSystem (LPASS) device tree infrastructure
for Maili, mirroring the Hawi SoC, so the ADSP-based audio pipeline can
be described by boards.

This adds under the ADSP GLINK edge the GPR (Generic Packet Router)
node with the q6apm and q6prm services, and on the SoC bus the RX, TX
and VA Bolero macro codecs, their RX/TX SoundWire controllers, the VA
CSR heartbeat clock provider, and the LPASS LPI TLMM pinctrl node with
the DMIC, I2S and SoundWire pin states used by the audio blocks.

The SoundWire controllers are left status = "disabled" here; boards
enable them once the attached codecs are described.
Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/maili.dtsi | 291 ++++++++++++++++++++++++++++
 1 file changed, 291 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/maili.dtsi b/arch/arm64/boot/dts/qcom/maili.dtsi
index 6053b61cab6f..d4267c22157b 100644
--- a/arch/arm64/boot/dts/qcom/maili.dtsi
+++ b/arch/arm64/boot/dts/qcom/maili.dtsi
@@ -20,6 +20,8 @@
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 #include "maili-ipcc.h"
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -4008,6 +4010,295 @@ compute-cb@8 {
 						dma-coherent;
 					};
 				};
+
+				gpr {
+					compatible = "qcom,gpr";
+					qcom,glink-channels = "adsp_apps";
+					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
+					qcom,intents = <512 20>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					q6apm: service@1 {
+						compatible = "qcom,q6apm";
+						reg = <GPR_APM_MODULE_IID>;
+						#sound-dai-cells = <0>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6apmbedai: bedais {
+							compatible = "qcom,q6apm-lpass-dais";
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#sound-dai-cells = <1>;
+						};
+
+						q6apmdai: dais {
+							compatible = "qcom,q6apm-dais";
+							iommus = <&apps_smmu 0x0c01 0x80>,
+								 <&apps_smmu 0x0c41 0x20>;
+						};
+					};
+
+					q6prm: service@2 {
+						compatible = "qcom,q6prm";
+						reg = <GPR_PRM_MODULE_IID>;
+						qcom,protection-domain = "avs/audio",
+									 "msm/adsp/audio_pd";
+
+						q6prmcc: clock-controller {
+							compatible = "qcom,q6prm-lpass-clocks";
+							#clock-cells = <2>;
+						};
+					};
+				};
+			};
+		};
+
+		lpass_rxmacro: codec@72c0000 {
+			compatible = "qcom,maili-lpass-rx-macro", "qcom,hawi-lpass-rx-macro";
+			reg = <0x0 0x072c0000 0x0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk", "lpr", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr1: soundwire@72d0000 {
+			compatible = "qcom,soundwire-v3.1.0";
+			reg = <0x0 0x072d0000 0x0 0x10000>;
+			interrupts = <GIC_ESPI 219 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&lpass_rxmacro>;
+			clock-names = "iface";
+			label = "RX";
+
+			pinctrl-0 = <&rx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <1>;
+			qcom,dout-ports = <11>;
+			qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+			qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		lpass_txmacro: codec@72e0000 {
+			compatible = "qcom,maili-lpass-tx-macro", "qcom,hawi-lpass-tx-macro";
+			reg = <0x0 0x72e0000 0x0 0x1000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_vamacro>;
+			clock-names = "mclk", "lpr", "dcodec", "fsgen";
+
+			#clock-cells = <0>;
+			clock-output-names = "mclk";
+			#sound-dai-cells = <1>;
+		};
+
+		swr2: soundwire@7e90000 {
+			compatible = "qcom,soundwire-v3.1.0";
+			reg = <0x0 0x7e90000 0x0 0x10000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "core", "wakeup";
+			clocks = <&lpass_txmacro>;
+			clock-names = "iface";
+			label = "TX";
+
+			pinctrl-0 = <&tx_swr_active>;
+			pinctrl-names = "default";
+
+			qcom,din-ports = <4>;
+			qcom,dout-ports = <0>;
+			qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x01 0x03>;
+			qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x00 0x01>;
+			qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+			qcom,ports-hstart = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-hstop = /bits/ 8 <0xff 0xff 0x0f 0xff>;
+			qcom,ports-word-length = /bits/ 8 <0xff 0x00 0x00 0xff>;
+			qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0x00 0xff>;
+			qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x01 0x00>;
+
+			#address-cells = <2>;
+			#size-cells = <0>;
+			#sound-dai-cells = <1>;
+
+			status = "disabled";
+		};
+
+		lpass_vamacro: codec@7ec0000 {
+			compatible = "qcom,maili-lpass-va-macro", "qcom,hawi-lpass-va-macro";
+			reg = <0x0 0x07ec0000 0x0 0x2000>;
+			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&lpass_va_csr>;
+			clock-names = "mclk", "lpr", "dcodec", "heartbeatpulse";
+
+			#clock-cells = <0>;
+			clock-output-names = "fsgen";
+			#sound-dai-cells = <1>;
+		};
+
+		lpass_va_csr: va-csr@7ee0000 {
+			compatible = "qcom,hawi-lpass-va-csr";
+			reg = <0x0 0x07ee0000 0x0 0xe000>;
+			clocks = <&q6prmcc LPASS_HW_LPR_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "lpr", "audio";
+			#clock-cells = <0>;
+		};
+
+		lpass_tlmm: pinctrl@7f60000 {
+			compatible = "qcom,hawi-lpass-lpi-pinctrl";
+			reg = <0x0 0x07f60000 0x0 0x20000>;
+
+			clocks = <&q6prmcc LPASS_HW_LPR_VOTE
+					  LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+			clock-names = "lpr", "audio";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+			dmic01_default: dmic01-default-state {
+				clk-pins {
+					pins = "gpio6";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio7";
+					function = "dmic1_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			dmic23_default: dmic23-default-state {
+				clk-pins {
+					pins = "gpio8";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio9";
+					function = "dmic2_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+
+			lpi_i2s1_active: lpi-i2s1-active-state {
+				clk-pins {
+					pins = "gpio10";
+					function = "i2s1_clk";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				ws-pins {
+					pins = "gpio11";
+					function = "i2s1_ws";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+
+				data-pins {
+					pins = "gpio15", "gpio16";
+					function = "i2s1_data";
+					drive-strength = <8>;
+					bias-disable;
+					output-high;
+				};
+			};
+
+			lpi_i2s1_sleep: lpi-i2s1-sleep-state {
+				clk-pins {
+					pins = "gpio10";
+					function = "i2s1_clk";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+
+				ws-pins {
+					pins = "gpio11";
+					function = "i2s1_ws";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+
+				data-pins {
+					pins = "gpio15", "gpio16";
+					function = "i2s1_data";
+					drive-strength = <2>;
+					bias-pull-down;
+					input-enable;
+				};
+			};
+
+			rx_swr_active: rx-swr-active-state {
+				clk-pins {
+					pins = "gpio3";
+					function = "swr_rx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio4", "gpio5";
+					function = "swr_rx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
+			};
+
+			tx_swr_active: tx-swr-active-state {
+				clk-pins {
+					pins = "gpio0";
+					function = "swr_tx_clk";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-disable;
+				};
+
+				data-pins {
+					pins = "gpio1", "gpio2", "gpio14";
+					function = "swr_tx_data";
+					drive-strength = <2>;
+					slew-rate = <1>;
+					bias-bus-hold;
+				};
 			};
 		};
 
-- 
2.34.1

[PATCH v1 7/8] arm64: dts: qcom: maili-mtp: enable audio playback and capture

[Prasad Kumpatla]

Wire up the audio use cases on the Maili MTP board on top of the LPASS
nodes added to the SoC dtsi, mirroring the Maili QRD board.

Add the sound card with the TDM playback, WCD playback/capture and VA
DMIC capture DAI links and the associated audio routing. Describe the
WCD9395 codec, enable the RX and TX SoundWire controllers with their
WCD RX/TX satellite ports, and add the WSA8855 speaker amplifier on
i2c3. Configure the VA macro DMIC supply and the required TLMM pin
states (WCD reset, WSA IRQ, WSA shutdown).

The MTP and QRD boards share the same SoC and PMIC rails, so the same
regulators (vreg_l2d_1p8, vreg_l4g_1p2, vreg_l15b_1p8, vreg_bob1,
vreg_l1g_1p2, vreg_l10b_1p8) and the pmh0110_f_e0_gpios speaker
shutdown GPIO from the shared pmh0110-kaanapali.dtsi apply unchanged.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/maili-mtp.dts | 206 +++++++++++++++++++++++++
 1 file changed, 206 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/maili-mtp.dts b/arch/arm64/boot/dts/qcom/maili-mtp.dts
index 1fdc91e03271..31192a01e70e 100644
--- a/arch/arm64/boot/dts/qcom/maili-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/maili-mtp.dts
@@ -7,9 +7,11 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/leds/common.h>
 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 #include "maili.dtsi"
 #include "pm8010-kaanapali.dtsi"	/* SPMI1: SID-C/D */
 #include "pmd8028-kaanapali.dtsi"	/* SPMI1: SID-4 */
@@ -126,6 +128,122 @@ pmic_glink_dp_out: endpoint {
 		};
 	};
 
+	maili_sound: sound {
+		compatible = "qcom,maili-sndcard", "qcom,sm8450-sndcard";
+		model = "MAILI-MTP";
+
+		audio-routing = "IN1_HPHL", "HPHL_OUT",
+				"IN2_HPHR", "HPHR_OUT",
+				"AMIC2", "MIC BIAS2",
+				"VA DMIC0", "MIC BIAS1",
+				"VA DMIC1", "MIC BIAS1",
+				"VA DMIC2", "MIC BIAS3",
+				"VA DMIC3", "MIC BIAS3",
+				"TX SWR_INPUT", "ADC2_OUTPUT";
+
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&lpi_i2s1_active>;
+		pinctrl-1 = <&lpi_i2s1_sleep>;
+
+		va-dmic-dai-link {
+			link-name = "VA DMIC Capture";
+
+			codec {
+				sound-dai = <&lpass_vamacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-capture-dai-link {
+			link-name = "WCD Capture";
+
+			codec {
+				sound-dai = <&wcd939x 1>, <&swr2 0>, <&lpass_txmacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wcd-playback-dai-link {
+			link-name = "WCD Playback";
+
+			codec {
+				sound-dai = <&wcd939x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+
+		wsa-playback-dai-link {
+			link-name = "WSA Playback";
+
+			codec {
+				sound-dai = <&wsa885x>;
+				dai-tdm-slot-num = <2>;
+				dai-tdm-slot-width = <32>;
+				dai-tdm-slot-rx-mask = <1 1>;
+			};
+
+			cpu {
+				sound-dai = <&q6apmbedai AIF_TDM_RX_1>;
+				dai-tdm-slot-num = <2>;
+				dai-tdm-slot-width = <32>;
+				dai-tdm-slot-rx-mask = <1 1>;
+			};
+
+			platform {
+				sound-dai = <&q6apm>;
+			};
+		};
+	};
+
+	wcd939x: audio-codec {
+		compatible = "qcom,wcd9395-codec", "qcom,wcd9390-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000
+							 500000 500000 500000 500000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>;
+
+		vdd-buck-supply = <&vreg_l15b_1p8>;
+		vdd-io-supply = <&vreg_l15b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob1>;
+		vdd-px-supply = <&vreg_l3f_1p2>;
+		vdd-rxtx-supply = <&vreg_l15b_1p8>;
+
+		#sound-dai-cells = <1>;
+	};
+
 	sdcard_vdd_3p0: sdcard-vdd-3p0 {
 		compatible = "regulator-fixed";
 
@@ -743,6 +861,70 @@ vreg_l7n_3p3: ldo7 {
 	};
 };
 
+&i2c3 {
+
+	status = "okay";
+
+	wsa885x: speaker@c {
+		compatible = "qcom,wsa8855";
+		reg = <0x0c>;
+
+		interrupt-parent = <&tlmm>;
+		interrupts = <98 IRQ_TYPE_EDGE_FALLING>;
+
+		pinctrl-0 = <&wsa885x_spkr_sd_n &wsa885x_irq_gpio>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&pmh0110_f_e0_gpios 11 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l2d_1p8>;
+		vdd-io-supply = <&vreg_l4g_1p2>;
+
+		qcom,battery-config = "1s";
+
+		#sound-dai-cells = <0>;
+
+		status = "okay";
+	};
+};
+
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+
+	vdd-micb-supply = <&vreg_l10b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&q6apmbedai {
+	dai@40 {
+		reg = <AIF_TDM_RX_1>;
+		clocks = <&q6prmcc LPASS_CLK_ID_QAIF_IF1_IBIT
+			  LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+		clock-names = "bclk";
+	};
+};
+
+&swr1 {
+	status = "okay";
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010e00";
+		reg = <0 4>;
+
+		qcom,rx-port-mapping = <1 2 3 4 5 9>;
+	};
+};
+
+&swr2 {
+	status = "okay";
+
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010e00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <3 3 3 4>;
+	};
+};
+
 &pcie0 {
 	status = "okay";
 };
@@ -820,6 +1002,16 @@ volume_up_n: volume-up-n-state {
 	};
 };
 
+&pmh0110_f_e0_gpios {
+	wsa885x_spkr_sd_n: wsa885x-spkr-sd-n-state {
+		pins = "gpio11";
+		function = "normal";
+		input-disable;
+		output-enable;
+		power-source = <1>; /* 1.8V */
+	};
+};
+
 &pmh0101_pwm {
 	status = "okay";
 
@@ -906,6 +1098,20 @@ &tlmm {
 			       <119 2>,	/* SoCCP */
 			       <144 2>,	/* CXM UART */
 			       <211 1>; /* NFC Secure IO */
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio161";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+	};
+
+	wsa885x_irq_gpio: wsa885x-irq-state {
+		pins = "gpio98";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
 };
 
 &uart7 {
-- 
2.34.1

[PATCH v1 8/8] arm64: defconfig: Enable Hawi LPASS LPI pinctrl driver

[Prasad Kumpatla]

Build the LPASS LPI pinctrl driver as module, as required by the Hawi
and Maili platforms to control all the LPI GPIOs.

Signed-off-by: Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5217de386edc..5e76b86d25cc 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -702,6 +702,7 @@ CONFIG_PINCTRL_IMX_SCMI=y
 CONFIG_PINCTRL_IMX91=y
 CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
 CONFIG_PINCTRL_LPASS_LPI=m
+CONFIG_PINCTRL_HAWI_LPASS_LPI=m
 CONFIG_PINCTRL_MILOS_LPASS_LPI=m
 CONFIG_PINCTRL_SC7280_LPASS_LPI=m
 CONFIG_PINCTRL_SM6115_LPASS_LPI=m
-- 
2.34.1

Re: [PATCH v1 3/8] ASoC: dt-bindings: qcom: Add Maili LPASS macro codecs

[Krzysztof Kozlowski]

On 23/09/2026 10:46, Prasad Kumpatla wrote:
> diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
> index 6aa8ccd60c01..de65a3159380 100644
> --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
> +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml
> @@ -29,6 +29,9 @@ properties:
>                - qcom,sm8750-lpass-rx-macro
>                - qcom,x1e80100-lpass-rx-macro
>            - const: qcom,sm8550-lpass-rx-macro
> +      - items:
> +          - const: qcom,maili-lpass-rx-macro
> +          - const: qcom,hawi-lpass-rx-macro


You miss hawi compatible used alone. At least on a next from a 18th.

Best regards,
Krzysztof

Re: [PATCH v1 0/8] ASoC: qcom: Add audio support for Hawi and Maili platforms

[Mark Brown]

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On Wed, Sep 23, 2026 at 02:16:19PM +0530, Prasad Kumpatla wrote:

> base-commit: 6c58e38b255a3e0c11e513e3b8de85eb26fb02b5
> prerequisite-patch-id: e6735f29343dd80d0e7ad48b6874eab4a5d7efc6
> prerequisite-patch-id: ac7bc5ad958bb392a57871dde1f79c2fc520d482
> prerequisite-patch-id: 332b888996b9d6c58e8c90eada37dc14137755ea
> prerequisite-patch-id: 21e9dfd02f282ea4239f12d91ac8a2be76aaad29
> prerequisite-patch-id: 52f17e16e09853e366ecc3da2676654df79daf06
> prerequisite-patch-id: f0b1cd1f1f8daf0e1814a338446d493d64c9469f
> prerequisite-patch-id: 29a1620a2ea61c0b7b052220e5ea522b1fbf2ad8
> prerequisite-patch-id: 0872295385e6712bf342d84f095ec3710abde8d8
> prerequisite-patch-id: 69807d41bbbd6177da4374639ae280501f3f60df
> prerequisite-patch-id: d9f8613cac873926d6d2fd77e45002d34954b434
> prerequisite-patch-id: 446fe28b27dbf5ce4240704d89296a5af69e8b21
> prerequisite-patch-id: dc5ac9645789f25b3742dc4fca08dab4c1e4826d
> prerequisite-patch-id: 0521512205679cad2462ecda959239aadc48cce6

As I have repeatedly told Qualcomm people please stop sending me patches
that don't apply, please collaborate with your colleagues to get
whatever it is you depend on merged and once that has happened send your
new stuff.  Qualcomm is sending a very high volume of patches, they seem
to get limited review from other Qualcomm people and progress very
slowly.  I'm getting a lot of Qualcomm code sent to me, in hard to
manage forms.  Please also consider helping out with review of other
code, not just submitting your own.  This is not directed to you
specifically, this is more Qualcomm as a whole.

I've dropped this for now, please resend once it can at least be
applied.

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