[PATCH 0/2] usb: fix ASM3242 reporting SuperSpeed for a Gen 2x2 link

[PATCH 0/2] usb: fix ASM3242 reporting SuperSpeed for a Gen 2x2 link

[Kean Ren]

The ASMedia ASM3242 (1b21:3242) reports the SuperSpeed speed ID together
with two active lanes for a link that is actually running at USB 3.2
Gen 2x2 after a cold boot.  Linux therefore classifies the device as
USB 3.0 SuperSpeed and reports 5000M/x2, although the measured
throughput is 1.49-1.60 GB/s (11.9-12.8 Gbps), which is above the
physical ceiling of a 10 Gbps link (~1.25 GB/s).

  Patch 1 is a generic correctness fix: get_port_ssp_rate() currently
  cannot recognise USB 3.2 Gen 1x2 at all, because it rejects any
  matching sublink entry whose link protocol is not SuperSpeedPlus
  before it looks at the number of active lanes.

  Patch 2 adds a controller quirk so that this hardware reports the
  Gen 2x2 speed ID.  The raw extended port status, the measured
  throughput and the list of resets that do and do not restore the
  correct report are all in the patch description.

The wrong report is 100% reproducible after every reboot and is only
cleared by an S3 suspend/resume.  Raw data (lsusb -v, lspci -vv, sysfs
and BOS dumps, kernel log) is available on request.

Kean Ren (2):
  usb: core: hub: recognise two-lane SuperSpeed sublinks as Gen 1x2
  xhci: fix ASM3242 port speed report for Gen 2x2 links after cold boot

 drivers/usb/core/hub.c      | 30 ++++++++++++++++++++----------
 drivers/usb/host/xhci-hub.c | 17 +++++++++++++++--
 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.h     |  1 +
 4 files changed, 40 insertions(+), 12 deletions(-)

[PATCH 1/2] usb: core: hub: recognise two-lane SuperSpeed sublinks as Gen 1x2

[Kean Ren]

get_port_ssp_rate() rejects every matching sublink speed attribute whose
link protocol (LP) is not SuperSpeedPlus by jumping to the "unknown"
exit before it looks at the number of active lanes.

USB 3.2 Gen 1x2 runs two SuperSpeed (Gen 1) lanes, so the matching
sublink entry advertises LP = SuperSpeed while two lanes are in use.
The current code therefore returns USB_SSP_GEN_UNKNOWN for such a link
and the USB core falls back to USB_SPEED_SUPER, reporting 5000 Mbps.

Handle the two-lane cases before rejecting non-SuperSpeedPlus entries:

  >= 10 Gbps per lane and 2 lanes -> USB_SSP_GEN_2x2
  >=  5 Gbps per lane and 2 lanes -> USB_SSP_GEN_1x2

so that a genuine Gen 1x2 link is reported as 10000 Mbps instead of
5000 Mbps.

Signed-off-by: Kean Ren <rh_king@163.com>
---
 drivers/usb/core/hub.c | 30 ++++++++++++++++++++----------
 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 3345b3298daf..50f14dd6a41f 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -2866,10 +2866,6 @@ static enum usb_ssp_rate get_port_ssp_rate(struct usb_device *hdev,
 			    type == USB_SSP_SUBLINK_SPEED_ST_ASYM_TX)
 				goto out;
 
-			if (FIELD_GET(USB_SSP_SUBLINK_SPEED_LP, attr) !=
-			    USB_SSP_SUBLINK_SPEED_LP_SSP)
-				goto out;
-
 			lse = FIELD_GET(USB_SSP_SUBLINK_SPEED_LSE, attr);
 			mantissa = FIELD_GET(USB_SSP_SUBLINK_SPEED_LSM, attr);
 
@@ -2877,14 +2873,28 @@ static enum usb_ssp_rate get_port_ssp_rate(struct usb_device *hdev,
 			for (; lse < USB_SSP_SUBLINK_SPEED_LSE_GBPS; lse++)
 				mantissa /= 1000;
 
-			if (mantissa >= 10 && lanes == 1)
-				return USB_SSP_GEN_2x1;
+			/*
+			 * Two active lanes mean USB 3.2 dual-lane operation.
+			 * A Gen 1x2 link uses SuperSpeed (Gen 1) signalling on
+			 * both lanes, so its sublink entry advertises the
+			 * SuperSpeed link protocol rather than SuperSpeedPlus.
+			 * Handle the two-lane cases before rejecting entries
+			 * that do not advertise SuperSpeedPlus.
+			 */
+			if (lanes == 2) {
+				if (mantissa >= 10)
+					return USB_SSP_GEN_2x2;
+				if (mantissa >= 5)
+					return USB_SSP_GEN_1x2;
+				goto out;
+			}
 
-			if (mantissa >= 10 && lanes == 2)
-				return USB_SSP_GEN_2x2;
+			if (FIELD_GET(USB_SSP_SUBLINK_SPEED_LP, attr) !=
+			    USB_SSP_SUBLINK_SPEED_LP_SSP)
+				goto out;
 
-			if (mantissa >= 5 && lanes == 2)
-				return USB_SSP_GEN_1x2;
+			if (mantissa >= 10)
+				return USB_SSP_GEN_2x1;
 
 			goto out;
 		}

[PATCH 2/2] xhci: fix ASM3242 port speed report for Gen 2x2 links after cold boot

[Kean Ren]

The ASMedia ASM3242 (1b21:3242) reports the SuperSpeed speed ID (4) in
PORTSC[13:10], together with two active lanes, for a link that is
actually running at Gen 2x2 after a cold boot.
xhci_get_ext_port_status() copies that ID into dwExtPortStatus, so the
USB core matches SSID 4 (whose LP is SuperSpeed, not SuperSpeedPlus),
returns USB_SSP_GEN_UNKNOWN and falls back to USB_SPEED_SUPER:

  $ lsusb -t
      |__ Port 001: Dev 002, If 0, Class=Mass Storage, Driver=uas, 5000M/x2
  $ cat /sys/bus/usb/devices/2-1/speed
  5000

while the link really runs at 20 Gbps:

  GetPortStatus(HUB_EXT_PORT_STATUS) -> dwExtPortStatus = 0x00001144
      (RX/TX speed id 4, RX/TX lanes 2)     after a cold boot
  GetPortStatus(HUB_EXT_PORT_STATUS) -> dwExtPortStatus = 0x00001177
      (RX/TX speed id 7, RX/TX lanes 2)     after an S3 resume

  O_DIRECT throughput, cross-checked with /proc/diskstats:
      1.49 - 1.60 GB/s (11.9 - 12.8 Gbps)  in the "5000M" state
      1.63 - 1.83 GB/s (13.0 - 14.7 Gbps)  in the "20000M" state

Both exceed the physical ceiling of a 10 Gbps link (~1.25 GB/s), so the
link is Gen 2x2 in both states and only the controller's report is
wrong.  Only an S3 suspend/resume makes the controller report speed ID
7; a device re-plug, a port disable/enable, an xhci_hcd unbind/bind, a
PCI function reset and a PCI remove+rescan all leave the wrong value in
place.

Add XHCI_ASM3242_SPEED_QUIRK and, when it is set, report the Gen 2x2
speed ID when the controller reports SuperSpeed with two active lanes.

Reported-by: Kean Ren <rh_king@163.com>
Link: https://lore.kernel.org/linux-usb/<your-report-message-id>/
Signed-off-by: Kean Ren <rh_king@163.com>
---
 drivers/usb/host/xhci-hub.c | 17 +++++++++++++++--
 drivers/usb/host/xhci-pci.c |  4 ++++
 drivers/usb/host/xhci.h     |  1 +
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 470bafe1802b..ef2b35b31492 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -1001,13 +1001,26 @@ static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 	return 0;
 }
 
-static u32 xhci_get_ext_port_status(u32 portsc, u32 port_li)
+static u32 xhci_get_ext_port_status(struct xhci_hcd *xhci, u32 portsc,
+				    u32 port_li)
 {
 	u32 ext_stat = 0;
 	int speed_id;
 
 	/* only support rx and tx lane counts of 1 in usb3.1 spec */
 	speed_id = DEV_PORT_SPEED(portsc);
+
+	/*
+	 * The ASM3242 reports the SuperSpeed speed ID (4) together with two
+	 * active lanes for a link that is actually running at Gen 2x2 after a
+	 * cold boot.  Reporting that ID makes the USB core fall back to
+	 * USB_SPEED_SUPER (5000 Mbps) although the link runs at 20 Gbps, so
+	 * report the Gen 2x2 speed ID (7) instead.
+	 */
+	if ((xhci->quirks & XHCI_ASM3242_SPEED_QUIRK) && speed_id == 4 &&
+	    PORT_RX_LANES(port_li) && PORT_TX_LANES(port_li))
+		speed_id = 7;
+
 	ext_stat |= speed_id;		/* bits 3:0, RX speed id */
 	ext_stat |= speed_id << 4;	/* bits 7:4, TX speed id */
 
@@ -1265,7 +1278,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 				break;
 			}
 			port_li = readl(&port->port_reg->portli);
-			status = xhci_get_ext_port_status(portsc, port_li);
+			status = xhci_get_ext_port_status(xhci, portsc, port_li);
 			put_unaligned_le32(status, &buf[4]);
 		}
 		break;
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index a8889081ae82..6219151d9eb0 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -471,6 +471,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
 	     pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
 		xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
+	    pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)
+		xhci->quirks |= XHCI_ASM3242_SPEED_QUIRK;
+
 	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 		xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index c7bfa7f028d3..77fab2f29693 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1647,6 +1647,7 @@ struct xhci_hcd {
 #define XHCI_CDNS_SCTX_QUIRK	BIT_ULL(48)
 #define XHCI_ETRON_HOST	BIT_ULL(49)
 #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
+#define XHCI_ASM3242_SPEED_QUIRK	BIT_ULL(51)
 
 	unsigned int		num_active_eps;
 	unsigned int		limit_active_eps;

Re: [PATCH 1/2] usb: core: hub: recognise two-lane SuperSpeed sublinks as Gen 1x2

[Thinh Nguyen]

On Sun, Sep 20, 2026, Kean Ren wrote:
> get_port_ssp_rate() rejects every matching sublink speed attribute whose
> link protocol (LP) is not SuperSpeedPlus by jumping to the "unknown"
> exit before it looks at the number of active lanes.
> 
> USB 3.2 Gen 1x2 runs two SuperSpeed (Gen 1) lanes, so the matching

Gen 1x2 is SuperSpeed Plus and should use LP = SSP

> sublink entry advertises LP = SuperSpeed while two lanes are in use.
> The current code therefore returns USB_SSP_GEN_UNKNOWN for such a link
> and the USB core falls back to USB_SPEED_SUPER, reporting 5000 Mbps.
> 
> Handle the two-lane cases before rejecting non-SuperSpeedPlus entries:
> 
>   >= 10 Gbps per lane and 2 lanes -> USB_SSP_GEN_2x2
>   >=  5 Gbps per lane and 2 lanes -> USB_SSP_GEN_1x2
> 
> so that a genuine Gen 1x2 link is reported as 10000 Mbps instead of
> 5000 Mbps.
> 
> Signed-off-by: Kean Ren <rh_king@163.com>


Gen 1x2 is a SuperSpeed Plus mode and should advertise LP =
USB_SSP_SUBLINK_SPEED_LP_SSP. A controller reporting Gen 1x2 with LP =
SuperSpeed is violating the expected encoding.

This should be handled as a controller-specific quirk and not by
relaxing the generic USB core parsing.

BR,
Thinh

Re: [PATCH 2/2] xhci: fix ASM3242 port speed report for Gen 2x2 links after cold boot

[Michal Pecio]

On Sun, 20 Sep 2026 10:52:43 +0800, Kean Ren wrote:
> The ASMedia ASM3242 (1b21:3242) reports the SuperSpeed speed ID (4) in
> PORTSC[13:10], together with two active lanes, for a link that is
> actually running at Gen 2x2 after a cold boot.
> xhci_get_ext_port_status() copies that ID into dwExtPortStatus, so the
> USB core matches SSID 4 (whose LP is SuperSpeed, not SuperSpeedPlus),
> returns USB_SSP_GEN_UNKNOWN and falls back to USB_SPEED_SUPER:
> 
>   $ lsusb -t
>       |__ Port 001: Dev 002, If 0, Class=Mass Storage, Driver=uas, 5000M/x2
>   $ cat /sys/bus/usb/devices/2-1/speed
>   5000
> 
> while the link really runs at 20 Gbps:
> 
>   GetPortStatus(HUB_EXT_PORT_STATUS) -> dwExtPortStatus = 0x00001144
>       (RX/TX speed id 4, RX/TX lanes 2)     after a cold boot
>   GetPortStatus(HUB_EXT_PORT_STATUS) -> dwExtPortStatus = 0x00001177
>       (RX/TX speed id 7, RX/TX lanes 2)     after an S3 resume
> 
>   O_DIRECT throughput, cross-checked with /proc/diskstats:
>       1.49 - 1.60 GB/s (11.9 - 12.8 Gbps)  in the "5000M" state
>       1.63 - 1.83 GB/s (13.0 - 14.7 Gbps)  in the "20000M" state
> 
> Both exceed the physical ceiling of a 10 Gbps link (~1.25 GB/s), so the
> link is Gen 2x2 in both states and only the controller's report is
> wrong.  Only an S3 suspend/resume makes the controller report speed ID
> 7; a device re-plug, a port disable/enable, an xhci_hcd unbind/bind, a
> PCI function reset and a PCI remove+rescan all leave the wrong value in
> place.

Out of curiosity, does it mean that after one suspend cycle the
controller begins to work normally and reports correct speed for
new devices too, or only for those present during resume?

> Add XHCI_ASM3242_SPEED_QUIRK and, when it is set, report the Gen 2x2
> speed ID when the controller reports SuperSpeed with two active lanes.
> 
> Reported-by: Kean Ren <rh_king@163.com>
> Link: https://lore.kernel.org/linux-usb/<your-report-message-id>/
> Signed-off-by: Kean Ren <rh_king@163.com>
> ---
>  drivers/usb/host/xhci-hub.c | 17 +++++++++++++++--
>  drivers/usb/host/xhci-pci.c |  4 ++++
>  drivers/usb/host/xhci.h     |  1 +
>  3 files changed, 20 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
> index 470bafe1802b..ef2b35b31492 100644
> --- a/drivers/usb/host/xhci-hub.c
> +++ b/drivers/usb/host/xhci-hub.c
> @@ -1001,13 +1001,26 @@ static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
>  	return 0;
>  }
>  
> -static u32 xhci_get_ext_port_status(u32 portsc, u32 port_li)
> +static u32 xhci_get_ext_port_status(struct xhci_hcd *xhci, u32 portsc,
> +				    u32 port_li)
>  {
>  	u32 ext_stat = 0;
>  	int speed_id;
>  
>  	/* only support rx and tx lane counts of 1 in usb3.1 spec */
>  	speed_id = DEV_PORT_SPEED(portsc);
> +
> +	/*
> +	 * The ASM3242 reports the SuperSpeed speed ID (4) together with two
> +	 * active lanes for a link that is actually running at Gen 2x2 after a
> +	 * cold boot.  Reporting that ID makes the USB core fall back to
> +	 * USB_SPEED_SUPER (5000 Mbps) although the link runs at 20 Gbps, so
> +	 * report the Gen 2x2 speed ID (7) instead.
> +	 */
> +	if ((xhci->quirks & XHCI_ASM3242_SPEED_QUIRK) && speed_id == 4 &&
> +	    PORT_RX_LANES(port_li) && PORT_TX_LANES(port_li))
> +		speed_id = 7;

Is there any way to distinguish 2x2 from 1x2 here? If 1x2 gets the same
bogus Speed ID as 2x2, this will incorrectly report it as 2x2, right?

> +
>  	ext_stat |= speed_id;		/* bits 3:0, RX speed id */
>  	ext_stat |= speed_id << 4;	/* bits 7:4, TX speed id */
>  
> @@ -1265,7 +1278,7 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
>  				break;
>  			}
>  			port_li = readl(&port->port_reg->portli);
> -			status = xhci_get_ext_port_status(portsc, port_li);
> +			status = xhci_get_ext_port_status(xhci, portsc, port_li);
>  			put_unaligned_le32(status, &buf[4]);
>  		}
>  		break;
> diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
> index a8889081ae82..6219151d9eb0 100644
> --- a/drivers/usb/host/xhci-pci.c
> +++ b/drivers/usb/host/xhci-pci.c
> @@ -471,6 +471,10 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
>  	     pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
>  		xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
>  
> +	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
> +	    pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI)
> +		xhci->quirks |= XHCI_ASM3242_SPEED_QUIRK;
> +
>  	if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
>  		pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
>  		xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index c7bfa7f028d3..77fab2f29693 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1647,6 +1647,7 @@ struct xhci_hcd {
>  #define XHCI_CDNS_SCTX_QUIRK	BIT_ULL(48)
>  #define XHCI_ETRON_HOST	BIT_ULL(49)
>  #define XHCI_LIMIT_ENDPOINT_INTERVAL_9 BIT_ULL(50)
> +#define XHCI_ASM3242_SPEED_QUIRK	BIT_ULL(51)
>  
>  	unsigned int		num_active_eps;
>  	unsigned int		limit_active_eps;
> 

Re: [PATCH 1/2] usb: core: hub: recognise two-lane SuperSpeed sublinks as Gen 1x2

[Michal Pecio]

On Thu, 24 Sep 2026 02:06:12 +0000, Thinh Nguyen wrote:
> On Sun, Sep 20, 2026, Kean Ren wrote:
> > get_port_ssp_rate() rejects every matching sublink speed attribute
> > whose link protocol (LP) is not SuperSpeedPlus by jumping to the
> > "unknown" exit before it looks at the number of active lanes.
> > 
> > USB 3.2 Gen 1x2 runs two SuperSpeed (Gen 1) lanes, so the matching  
> 
> Gen 1x2 is SuperSpeed Plus and should use LP = SSP
> 
> > sublink entry advertises LP = SuperSpeed while two lanes are in use.
> > The current code therefore returns USB_SSP_GEN_UNKNOWN for such a
> > link and the USB core falls back to USB_SPEED_SUPER, reporting 5000
> > Mbps.
> > 
> > Handle the two-lane cases before rejecting non-SuperSpeedPlus
> > entries: 
> >   >= 10 Gbps per lane and 2 lanes -> USB_SSP_GEN_2x2
> >   >=  5 Gbps per lane and 2 lanes -> USB_SSP_GEN_1x2  
> > 
> > so that a genuine Gen 1x2 link is reported as 10000 Mbps instead of
> > 5000 Mbps.

Was it tested with a genuine Gen 1x2 device? On which hub?

> > 
> > Signed-off-by: Kean Ren <rh_king@163.com>  
> 
> 
> Gen 1x2 is a SuperSpeed Plus mode and should advertise LP =
> USB_SSP_SUBLINK_SPEED_LP_SSP. A controller reporting Gen 1x2 with LP =
> SuperSpeed is violating the expected encoding.

This deals with the bmSublinkSpeedAttr array of hub BOS descriptor.
For host controller root hubs it's generated by xhci-hub.c.

And I think that the code which generates it already tries to avoid
setting SS (non-P) in multi-lane speeds, so what triggers this bug?

Regards,
Michal