From: Drew Fustini <fustini@kernel.org>
To: yunhui cui <cuiyunhui@bytedance.com>
Cc: "Adrien Ricciardi" <aricciardi@baylibre.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Atish Patra" <atish.patra@linux.dev>,
"Babu Moger" <babu.moger@amd.com>,
"Ben Horgan" <ben.horgan@arm.com>,
"Borislav Petkov" <bp@alien8.de>,
"Chen Pei" <cp0613@linux.alibaba.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
"Dave Martin" <Dave.Martin@arm.com>,
"Fenghua Yu" <fenghuay@nvidia.com>,
"Gong Shuai" <gong.shuai@sanechips.com.cn>,
"Gong Shuai" <gsh517@gmail.com>,
guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
liu.qingtao2@zte.com.cn,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Peter Newman" <peternewman@google.com>,
"Radim Krčmář" <rkrcmar@ventanamicro.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Rob Herring" <robh@kernel.org>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
"Clark Williams" <clrkwllms@kernel.org>,
"Steven Rostedt" <rostedt@goodmis.org>,
"Tony Luck" <tony.luck@intel.com>,
"Vasudevan Srinivasan" <vasu@rivosinc.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
x86@kernel.org, devicetree@vger.kernel.org,
linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org
Subject: Re: [PATCH v8 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask
Date: Thu, 24 Sep 2026 17:29:05 -0700 [thread overview]
Message-ID: <arXAUafBYERE7clK@thelio> (raw)
In-Reply-To: <CAEEQ3w=pDjEGfMtHUamxLFa0+qYuZ=od0OhAUH7_h+ybMAiO4g@mail.gmail.com>
On Wed, Sep 23, 2026 at 05:13:15PM +0800, yunhui cui wrote:
> Hi Fustini,
>
> On Fri, Sep 18, 2026 at 12:41 AM Drew Fustini <fustini@kernel.org> wrote:
> >
> > Wire CBQRI capacity controllers into resctrl as RDT_RESOURCE_L2 and
> > RDT_RESOURCE_L3 schemata.
> >
> > resctrl exposes a single capacity mask per resource, so when more than
> > one capacity controller backs a cache level they must report the same
> > number of capacity blocks. The same holds for the other capabilities
> > resctrl exposes once per resource. A level whose controllers disagree
> > is left unexposed. Other levels are unaffected.
> >
> > Control domains are created in the cpuhp online callback and keyed on
> > the onlining CPU's cache id from cacheinfo, so a CPU that is offline at
> > probe time still joins its domain once it comes online. A domain is
> > published on the ctrl_domains RCU list only after it is fully
> > initialized and brought online, and removed from the list before it is
> > taken offline, following the documented safe traversal rules.
> >
> > Assisted-by: LLM
> > Tested-by: Chen Pei <cp0613@linux.alibaba.com>
> > Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> > MAINTAINERS | 2 +
> > arch/riscv/include/asm/resctrl.h | 147 ++++++++
> > drivers/resctrl/Kconfig | 4 +
> > drivers/resctrl/Makefile | 1 +
> > drivers/resctrl/cbqri_resctrl.c | 785 +++++++++++++++++++++++++++++++++++++++
> > 5 files changed, 939 insertions(+)
[..]
> > diff --git a/drivers/resctrl/cbqri_resctrl.c b/drivers/resctrl/cbqri_resctrl.c
[..]
> > +/*
> > + * Note about terminology between x86 (Intel RDT/AMD QoS) and RISC-V:
> > + * CLOSID on x86 is RCID on RISC-V
> > + * RMID on x86 is MCID on RISC-V
> > + */
> > +u32 resctrl_arch_get_num_closid(struct rdt_resource *res)
> > +{
> > + struct cbqri_resctrl_res *hw_res;
> > +
> > + hw_res = container_of(res, struct cbqri_resctrl_res, resctrl_res);
> > +
> > + if (!hw_res->ctrl)
> > + return 0;
> > +
> > + return hw_res->ctrl->rcid_count;
> > +}
>
> When CDP is enabled, the resctrl core halves the value returned by
> resctrl_arch_get_num_closid(). Is that correct for CBQRI?
> CBQRI v1.0 defines allocation using an (RCID, AT) pair, and its example
> uses the same RCID=5 for separate AT=0 and AT=1 allocations.
>
> Thanks,
> Yunhui
You're right that this is not needed for RISC-V. CDP is still functional
but the upper half of RCIDs is unused.
It would require an fs/resctrl change to make the halving conditional.
Therefore, I would like to deal with that in a separate series and not
expand the scope of this series. I will add a comment above
resctrl_arch_get_num_closid() for v9, so the current situation is
obvious.
Thanks,
Drew
next prev parent reply other threads:[~2026-09-25 0:29 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-17 16:39 [PATCH v8 0/5] riscv: Add initial CBQRI resctrl support Drew Fustini
2026-09-17 16:39 ` [PATCH v8 1/5] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-09-17 16:39 ` [PATCH v8 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-09-17 16:57 ` sashiko-bot
2026-09-17 19:59 ` Drew Fustini
2026-09-18 0:54 ` Reinette Chatre
2026-09-22 6:57 ` Drew Fustini
2026-09-23 16:21 ` Reinette Chatre
2026-09-23 9:13 ` [External] " yunhui cui
2026-09-25 0:29 ` Drew Fustini [this message]
2026-09-17 16:39 ` [PATCH v8 3/5] riscv_cbqri: Make RESCTRL_FS available on RISC-V Drew Fustini
2026-09-17 16:39 ` [PATCH v8 4/5] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-09-17 16:39 ` [PATCH v8 5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
2026-09-17 17:11 ` sashiko-bot
2026-09-18 20:10 ` Drew Fustini
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