From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Paul Louvel <paul.louvel@bootlin.com>
Cc: Borislav Petkov <bp@alien8.de>, Tony Luck <tony.luck@intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-edac@vger.kernel.org, devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Herve Codina <herve.codina@bootlin.com>
Subject: Re: [PATCH v3 2/3] EDAC/cadence: Add Cadence DDR EDAC driver
Date: Fri, 25 Sep 2026 14:02:11 +0200 [thread overview]
Message-ID: <arZiv20Z4P7DQaD6@shikoro> (raw)
In-Reply-To: <20260924-paul-v7-3-rc1-edac-v3-2-bd8054a5b180@bootlin.com>
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Hi Paul,
thanks for your patches!
On Thu, Sep 24, 2026 at 04:12:48PM +0200, Paul Louvel wrote:
> Add the Cadence EDAC driver found on Renesas RZ/N1x SoC.
> The memory controller supports ECC, software scrubbing, and SECDED.
>
> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@bootlin.com>
Disclaimer: I don't know the technology nor the subsystem. So, only some
high level comments.
> +
> +static void cdns_rmw(struct cdns_mc_priv *priv, u32 reg, u32 mask, u32 val)
> +{
> + u32 regval;
> +
> + mutex_lock(&priv->lock);
> + regval = readl(priv->io_base + reg);
> + FIELD_MODIFY(mask, ®val, val);
> + writel(regval, priv->io_base + reg);
> + mutex_unlock(&priv->lock);
Hmm, a spinlock is probably more suitable for such short operations? You
could even save a lock here and use a generic mutex in
inject_ctrl_store() for the whole operation. That would work for now. In
terms of defensive programming, a spinlock could be argued, too, to make
future additions more robust.
> +static void cdns_mc_err_inject(struct mem_ctl_info *mci, u16 synd)
> +{
> + struct cdns_mc_priv *priv = mci->pvt_info;
> +
> + cdns_rmw(priv, CDNS_DDR_ECC_XOR, CDNS_DDR_ECC_XOR_CHECK_BITS, synd);
> + cdns_rmw(priv, CDNS_DDR_ECC_STAT, CDNS_DDR_ECC_STAT_FWC, 1);
> +}
Bike shedding: I think this is too short for a seperate function and it
should be folded into its caller.
> +
> +static ssize_t inject_ctrl_store(struct device *dev, struct device_attribute *attr, const char *buf,
> + size_t count)
> +{
> + struct mem_ctl_info *mci = to_mci(dev);
> + u16 synd;
> +
> + if (kstrtou16(buf, 16, &synd))
> + return -EINVAL;
> +
> + cdns_mc_err_inject(mci, synd);
> +
> + return count;
> +}
> +
> +static DEVICE_ATTR_WO(inject_ctrl);
> +
> +static struct attribute *cdns_edac_attrs[] = { &dev_attr_inject_ctrl.attr, NULL };
> +
> +ATTRIBUTE_GROUPS(cdns_edac);
What about using debugfs instead via edac_debugfs_create_*?
Happy hacking,
Wolfram
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next prev parent reply other threads:[~2026-09-25 12:02 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 14:12 [PATCH v3 0/3] Add Renesas RZ/N1x " Paul Louvel
2026-09-24 14:12 ` [PATCH v3 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC binding Paul Louvel
2026-09-25 12:30 ` Wolfram Sang
2026-09-25 12:50 ` Miquel Raynal
2026-09-25 12:57 ` Geert Uytterhoeven
2026-09-25 13:14 ` Miquel Raynal
2026-09-24 14:12 ` [PATCH v3 2/3] EDAC/cadence: Add Cadence DDR EDAC driver Paul Louvel
2026-09-25 12:02 ` Wolfram Sang [this message]
2026-09-24 14:12 ` [PATCH v3 3/3] ARM: dts: renesas: r9a06g032: add EDAC node Paul Louvel
2026-09-25 12:19 ` Wolfram Sang
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