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From: Xu Yilun <yilun.xu@linux.intel.com>
To: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Cc: Moritz Fischer <mdf@kernel.org>, Xu Yilun <yilun.xu@intel.com>,
	Tom Rix <trix@redhat.com>,
	linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] fpga: stratix10-soc: floor config_complete_timeout_us
Date: Mon, 28 Sep 2026 20:14:31 +0800	[thread overview]
Message-ID: <arpaJ7z+hOAASQMk@yilunxu-OptiPlex-7050> (raw)
In-Reply-To: <c2dce10175d54bd39fe3a9dd1a0ab783a62095f3.1790090287.git.adrian.ho.yin.ng@altera.com>

On Wed, Sep 23, 2026 at 12:02:43AM +0800, Adrian Ng Ho Yin wrote:
> Keep info->config_complete_timeout_us configurable. of-fpga-region
> leaves it at 0 when the DT property is absent, and usecs_to_jiffies(0)
> makes the wait return immediately. Reconfiguration also takes ~600ms in
> practice, so enforce S10_RECONFIG_TIMEOUT as a minimum floor while still
> honouring any larger caller-supplied value. Note this prevents a DT
> property from lowering the timeout below that floor.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> ---
>  drivers/fpga/stratix10-soc.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
> index c16ed571630b..83590e6b405f 100644
> --- a/drivers/fpga/stratix10-soc.c
> +++ b/drivers/fpga/stratix10-soc.c
> @@ -7,6 +7,7 @@
>  #include <linux/completion.h>
>  #include <linux/fpga/fpga-mgr.h>
>  #include <linux/firmware/intel/stratix10-svc-client.h>
> +#include <linux/minmax.h>
>  #include <linux/module.h>
>  #include <linux/of.h>
>  #include <linux/of_platform.h>
> @@ -360,7 +361,15 @@ static int s10_ops_write_complete(struct fpga_manager *mgr,
>  	unsigned long timeout;
>  	int ret;
>  
> -	timeout = usecs_to_jiffies(info->config_complete_timeout_us);
> +	/*
> +	 * Keep config_complete_timeout_us configurable. of-fpga-region leaves
> +	 * it at 0 when the DT property is absent, and usecs_to_jiffies(0)
> +	 * makes the wait return immediately. Reconfiguration also takes
> +	 * ~600ms in practice, so enforce S10_RECONFIG_TIMEOUT as a minimum
> +	 * floor while still honouring any larger caller-supplied value.
> +	 */
> +	timeout = max(usecs_to_jiffies(info->config_complete_timeout_us),
> +		      S10_RECONFIG_TIMEOUT);

Basically I think config_complete_timeout_us is used in a wrong way. You
can refer to other vendor fpga driver for reference.

>  
>  	do {
>  		reinit_completion(&priv->status_return_completion);
> -- 
> 2.49.GIT
> 
> 

  reply	other threads:[~2026-09-28 12:16 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 16:02 [PATCH 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout Adrian Ng Ho Yin
2026-09-22 16:02 ` [PATCH 1/3] fpga: stratix10-soc: always wait for svc buffer completion Adrian Ng Ho Yin
2026-09-22 16:02 ` [PATCH 2/3] fpga: stratix10-soc: prefer ERROR over BUFFER_DONE Adrian Ng Ho Yin
2026-09-28 11:59   ` Xu Yilun
2026-09-22 16:02 ` [PATCH 3/3] fpga: stratix10-soc: floor config_complete_timeout_us Adrian Ng Ho Yin
2026-09-28 12:14   ` Xu Yilun [this message]
2026-10-20  7:49 ` [PATCH v3 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout Adrian Ng Ho Yin
2026-10-20  7:49   ` [PATCH v3 1/3] fpga: stratix10-soc: always wait for svc buffer completion Adrian Ng Ho Yin
2026-10-20  7:49   ` [PATCH v3 2/3] fpga: stratix10-soc: use config_complete_timeout_us as a deadline Adrian Ng Ho Yin
2026-10-20  7:49   ` [PATCH v3 3/3] fpga: stratix10-soc: add SVC wait helper and prefer ERROR Adrian Ng Ho Yin

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