[PATCH v3 0/3] fpga: stratix10-soc: harden wait, ERROR order, and timeout

[Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>]

Stratix10 FPGA reconfiguration can fail or hang for three related
reasons in the FPGA manager. This series hardens s10_ops_write_init(),
s10_ops_write() and s10_ops_write_complete(). No dependency on the
stratix10-svc accumulate changes.

  1) always wait for svc buffer completion

     s10_ops_write() skips wait_for_completion_timeout() when
     priv->status is already set. Always call the wait; if complete()
     already ran, the done counter is raised and the wait returns
     immediately.

  2) use config_complete_timeout_us as a deadline

     config_complete_timeout_us was passed as the timeout of every wait
     for a service layer reply, so the value 0 that of-fpga-region
     leaves when the DT property is absent fails write_complete at once.
     Wait for each RECONFIG_STATUS reply with a driver timeout that
     covers the service layer's own polling window, and use
     config_complete_timeout_us only as the deadline for re-polling
     after a BUSY reply, as xilinx-core, efinix-spi and
     altera-pr-ip-core do. Because one reply can take up to the
     service layer polling window, the deadline is coarse.

  3) SVC wait helper; prefer ERROR over success bits

     Add s10_svc_wait() / s10_svc_send_and_wait(). write_init becomes
     one s10_svc_send_and_wait() call, write_complete uses it for each
     status request, and write() uses s10_svc_wait() after sending a
     data buffer or claim request. ERROR takes precedence over
     BUFFER_DONE, BUFFER_SUBMITTED, COMPLETED and OK in the accumulated
     status word.

Changes in v3:
  - Patch 2 replaces "floor config_complete_timeout_us": drop the max()
    floor, use config_complete_timeout_us as a re-poll deadline instead
    of the per-reply wait (Xu Yilun)
  - Patch 3 replaces "prefer ERROR over BUFFER_DONE": add the wait
    helpers and convert all three ops to them (Xu Yilun)
  - ERROR also wins over COMPLETED and OK (Xu Yilun)
  - Timeout patch moved before the helper patch so no intermediate
    commit can re-poll without a bound
  - write_complete ignores a stray wake-up from the last claim callback
    instead of counting it against the deadline
  - v2 was posted without a version tag as "[PATCH n/3]"

Adrian Ng Ho Yin (3):
  fpga: stratix10-soc: always wait for svc buffer completion
  fpga: stratix10-soc: use config_complete_timeout_us as a deadline
  fpga: stratix10-soc: add SVC wait helper and prefer ERROR

 drivers/fpga/stratix10-soc.c | 178 +++++++++++++++++++++--------------
 1 file changed, 106 insertions(+), 72 deletions(-)

-- 
2.49.GIT