Re: [PATCH v2 3/3] pwm: tegra: Implement .get_state()

["Uwe Kleine-König" <u.kleine-koenig@baylibre.com>]

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Hello Thierry,

On Tue, Sep 22, 2026 at 12:07:26PM +0200, Thierry Reding wrote:
> On Mon, Sep 21, 2026 at 04:26:03PM +0200, Uwe Kleine-König wrote:
> > On Mon, Sep 21, 2026 at 12:18:16PM +0200, Thierry Reding wrote:
> > > It feels like this has too many assumptions built-in. That's mostly a
> > > predefined issue, but I think if we want to get accurate hardware read-
> > > out, we need to address this.
> > > 
> > > According to the register documentation, the PWM depth is 16 bits wide
> > > (on generations where it can be programmed). The value defaults to 255
> > > (which is n - 1 encoded, hence TEGRA_PWM_DEPTH), but it can technically
> > > be reprogrammed to any 16-bit value, as far as I can tell.
> > > 
> > > So I think for this to be correct we'd need to read out the actual value
> > > before overwriting with TEGRA_PWM_CSR_0 contents above. At that point I
> > > think we'd need to either adjust the mask to be (2 * depth) - 1, or
> > > maybe better yet, avoid masking it out arbitrarily based on the depth
> > > and instead cap it at depth so we never exceed the 1:1 ratio for duty
> > > cycle vs. period.
> > 
> > As long as .apply() also hardcodes TEGRA_PWM_DEPTH, it's IMO fine that
> > .get_state() does so, too.
> 
> Okay, fair enough.

Is that an Ack then?

Best regards
Uwe

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