[PATCH v2 0/2] PCI: dwc: Support large BARs on UltraRISC DP1000

[PATCH v2 0/2] PCI: dwc: Support large BARs on UltraRISC DP1000

[Xincheng Zhang]

This series lets DWC host drivers skip generic outbound iATU programming
for host bridge MEM ranges, which is useful for some compute cards' very
large BAR size demand (>100GB).

DP1000 has 16 outbound iATU windows, and each window can map up to
4GB. This limits its allocatable MEM64 BAR size to 4GB*(16-3)=52GB
(-3 for CFG, I/O and MEM32).

But some EPs like compute cards demand large BAR size that exceeds the
mapping limit of the 13 iATUs. DWC IP spec allows RC to skip MEM iATU setup
and simply uses a direct mapping. By introducing a `bypass_ob_mem_iatu`
flag at the RC level, this patch enables large BARs on UR-DP1000
RISC-V CPU.

Tested on UltraRISC DP1000 EVB and Titan board. The system booted
successfully with PCIe links up on all three controllers and NVMe rootfs
mounted. MMIO read/write speed test within the large BAR space goes well.

Changes in v2:
- Validate skipped MEM ranges are identity-mapped before bypassing outbound
  iATU setup.
- Document the DWC PCIe RP Controller Databook v6.00a no-match pass-through
  behavior.
- Clarify that the DP1000 bypass is MEM-only; CFG and I/O iATU setup is
  unchanged.

Link: https://lore.kernel.org/r/20260827055448.1818858-1-zhangxincheng@ultrarisc.com

Xincheng Zhang (2):
  PCI: dwc: Allow drivers to skip MEM outbound iATU setup
  PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000

 .../pci/controller/dwc/pcie-designware-host.c   | 17 +++++++++++++++--
 drivers/pci/controller/dwc/pcie-designware.h    |  1 +
 drivers/pci/controller/dwc/pcie-ultrarisc.c     |  6 ++++++
 3 files changed, 22 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup

[Xincheng Zhang]

Some DWC-based controllers do not require outbound iATU windows for MEM
transactions. For those platforms, programming outbound iATU windows for
host bridge MEM ranges is unnecessary and may constrain the available MEM
aperture.

The DWC PCIe RP Controller Databook v6.00a, section 3.12.2, describes the
default outbound no-match behavior as pass-through. Section 3.12.5.6, "No
Address Match Result", says the address is not translated and programmable
TLP header fields come from the application transmit interface.

This no-match path cannot translate between different parent-bus and PCI
addresses, so require skipped MEM ranges to be identity-mapped.

Add dw_pcie_rp::bypass_ob_mem_iatu so drivers can skip generic MEM iATU
setup while using the common DWC host init path.

Existing drivers keep the current behavior because the flag defaults to
false. The I/O iATU setup does not use the MEM resource iterator, and the
iterator may be uninitialized when MEM setup is skipped. Avoid using it in
the I/O iATU error path.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
---
 .../pci/controller/dwc/pcie-designware-host.c   | 17 +++++++++++++++--
 drivers/pci/controller/dwc/pcie-designware.h    |  1 +
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index f5a38e6fd8d79..b06797b4e31d2 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -918,6 +918,20 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
 		atu.pci_addr = entry->res->start - entry->offset;
 
+		if (pp->bypass_ob_mem_iatu) {
+			/*
+			 * The no-match pass-through path preserves the correct
+			 * PCI address only for identity-mapped MEM ranges.
+			 */
+			if (atu.parent_bus_addr != atu.pci_addr) {
+				dev_err(pci->dev,
+					"Cannot bypass outbound iATU for non-identity MEM range %pr\n",
+					entry->res);
+				return -EINVAL;
+			}
+			continue;
+		}
+
 		/* Adjust iATU size if MSG TLP region was allocated before */
 		if (pp->msg_res && pp->msg_res->parent == entry->res)
 			res_size = resource_size(entry->res) -
@@ -964,8 +978,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 
 			ret = dw_pcie_prog_outbound_atu(pci, &atu);
 			if (ret) {
-				dev_err(pci->dev, "Failed to set IO range %pr\n",
-					entry->res);
+				dev_err(pci->dev, "Failed to set IO range\n");
 				return ret;
 			}
 			ob_iatu_index++;
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0735ae9409240..d89badcca2689 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -469,6 +469,7 @@ struct dw_pcie_rp {
 	struct pci_config_window *cfg;
 	bool			ecam_enabled;
 	bool			native_ecam;
+	bool			bypass_ob_mem_iatu;
 	bool                    skip_l23_ready;
 	bool			skip_pwrctrl_off;
 };
-- 
2.34.1

[PATCH v2 2/2] PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000

[Xincheng Zhang]

DP1000 has 16 outbound iATU windows and each window can map up to 4GB. One
window is used for CFG accesses, one for I/O space and one for the 32-bit
MEM aperture, leaving only 13 windows for the 64-bit MEM aperture.

This limits the 64-bit MEM aperture that can be described with outbound
iATU windows. DP1000 routes MEM transactions without using outbound iATU
windows, so skip generic DWC MEM outbound iATU setup to allow a larger
64-bit MEM aperture.

DP1000 does not use ECAM for this controller. Config space accesses keep
using the normal DWC config access path and CFG outbound iATU programming.
I/O space is also unchanged and still uses an outbound iATU window. The new
flag only skips generic MEM-window programming.

The DP1000 integration has SoC wrapper address decode for the PCIe MEM
apertures described by the "ranges" property. CPU physical accesses to
those MEM apertures are routed directly as PCIe MEM transactions with the
corresponding PCIe bus address, without consuming outbound iATU windows.

Set dw_pcie_rp::bypass_ob_mem_iatu for this controller.

Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
---
 drivers/pci/controller/dwc/pcie-ultrarisc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c
index 51e89180490d4..0d4989a0f3afc 100644
--- a/drivers/pci/controller/dwc/pcie-ultrarisc.c
+++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c
@@ -154,6 +154,12 @@ static int ultrarisc_pcie_probe(struct platform_device *pdev)
 
 	pp = &pci->pp;
 
+	/*
+	 * DP1000 routes MEM transactions without outbound iATU windows, which
+	 * avoids the 16-window/4GB-per-window aperture limit.
+	 */
+	pp->bypass_ob_mem_iatu = true;
+
 	platform_set_drvdata(pdev, ultra);
 
 	ret = ultrarisc_pcie_init_clks(ultra);
-- 
2.34.1

Re: [PATCH v2 0/2] PCI: dwc: Support large BARs on UltraRISC DP1000

[Manivannan Sadhasivam]

On Sat, 05 Sep 2026 10:56:33 +0800, Xincheng Zhang wrote:
> PCI: dwc: Support large BARs on UltraRISC DP1000
> 
> This series lets DWC host drivers skip generic outbound iATU programming
> for host bridge MEM ranges, which is useful for some compute cards' very
> large BAR size demand (>100GB).
> 
> DP1000 has 16 outbound iATU windows, and each window can map up to
> 4GB. This limits its allocatable MEM64 BAR size to 4GB*(16-3)=52GB
> (-3 for CFG, I/O and MEM32).
> 
> [...]

Applied, thanks!

[1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup
      commit: 35e7ff697f320aa4c0c8cd2f9d0377df307bb34a
[2/2] PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000
      commit: e9ad968d240e0d8313d3aac19bd5ef0dad866da1

Best regards,
-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup

[Niklas Cassel]

On Sat, Sep 05, 2026 at 10:56:34AM +0800, Xincheng Zhang wrote:
> Some DWC-based controllers do not require outbound iATU windows for MEM
> transactions. For those platforms, programming outbound iATU windows for
> host bridge MEM ranges is unnecessary and may constrain the available MEM
> aperture.
> 
> The DWC PCIe RP Controller Databook v6.00a, section 3.12.2, describes the
> default outbound no-match behavior as pass-through. Section 3.12.5.6, "No
> Address Match Result", says the address is not translated and programmable
> TLP header fields come from the application transmit interface.
> 
> This no-match path cannot translate between different parent-bus and PCI
> addresses, so require skipped MEM ranges to be identity-mapped.
> 
> Add dw_pcie_rp::bypass_ob_mem_iatu so drivers can skip generic MEM iATU
> setup while using the common DWC host init path.
> 
> Existing drivers keep the current behavior because the flag defaults to
> false. The I/O iATU setup does not use the MEM resource iterator, and the
> iterator may be uninitialized when MEM setup is skipped. Avoid using it in
> the I/O iATU error path.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> ---
>  .../pci/controller/dwc/pcie-designware-host.c   | 17 +++++++++++++++--
>  drivers/pci/controller/dwc/pcie-designware.h    |  1 +
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f5a38e6fd8d79..b06797b4e31d2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -918,6 +918,20 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
>  		atu.pci_addr = entry->res->start - entry->offset;
>  
> +		if (pp->bypass_ob_mem_iatu) {

Sorry for commenting on this patch after it was accepted.

But... since this behavior is intrinsic to the DWC controller, rather than
being SoC specific... Why bother creating a flag for it?

Is there a reason why this can't just be a simple:

if (atu.parent_bus_addr == atu.pci_addr)
	continue;

?


Kind regards,
Niklas

Re: [PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup

[Xincheng Zhang]

Hi Niklas,

On Wed, Oct 14, 2026 at 10:27:57AM +0200, Niklas Cassel wrote:
> Sorry for commenting on this patch after it was accepted.
>
> But... since this behavior is intrinsic to the DWC controller, rather than
> being SoC specific... Why bother creating a flag for it?
>
> Is there a reason why this can't just be a simple:
>
> if (atu.parent_bus_addr == atu.pci_addr)
> 	continue;

Thanks for pointing this out.

I added the flag because I had only tested no-match pass-through on DP1000.
But you are right that this is DWC behavior, not SoC-specific, and comparing
the two addresses is enough to tell whether translation is needed.

Since the series has already been applied, I will send a follow-up patch
that skips MEM outbound iATU programming when atu.parent_bus_addr is equal
to atu.pci_addr, and removes bypass_ob_mem_iatu and the UltraRISC-specific
setting. CFG and I/O accesses, as well as non-identity-mapped MEM ranges,
will continue to use outbound iATU windows.

Thanks,
Xincheng