Re: [PATCH] clk: qcom: negcc-nord: Keep the AHB2PHY_0 bridge clock always on

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Wed, Oct 07, 2026 at 03:31:46PM +0800, Shawn Guo wrote:
> NE_GCC_AHB2PHY_CLK gates the AHB2PHY_0 bridge, which fronts the
> USB2/USB3-DP PHYs, EUD and PHY_REFGEN_4. It has no consumer in DT, so
> clk_disable_unused() gates it before the PHY modules probe. The PHY
> initialization sequence then never reaches the PHYs, and DWC3 core soft
> reset times out:
> 
>   dwc3-qcom a600000.usb: DWC3 controller soft reset failed.
>   dwc3-qcom a600000.usb: error -ETIMEDOUT: failed to initialize core
> 
> As a result, USB on Nord only works when booting with clk_ignore_unused.
> EUD has no clock binding and may be accessed while the USB PHYs are
> powered down, so modelling the clock as a PHY consumer is not sufficient.
> 
> Mark the branch as always-on, as is done for the AHB2PHY clocks on
> other Qualcomm SoCs (e.g. Kuno, SDX75).
> 
> Assisted-by: LLM
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>

With an offline discussion, it's not desirable to keep AHB2PHY clock
always on. Please disregard this patch, and we will try to enable
the clock from USB PHY drivers.

Shawn

> ---
>  drivers/clk/qcom/negcc-nord.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c
> index 68ce4d6278ba..9c9b4a83df1c 100644
> --- a/drivers/clk/qcom/negcc-nord.c
> +++ b/drivers/clk/qcom/negcc-nord.c
> @@ -812,7 +812,7 @@ static struct clk_branch ne_gcc_ahb2phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(const struct clk_init_data) {
>  			.name = "ne_gcc_ahb2phy_clk",
> -			.ops = &clk_branch2_ops,
> +			.ops = &clk_branch2_aon_ops,
>  		},
>  	},
>  };
> -- 
> 2.43.0
>