[PATCH v4 00/13] Enable USB3 for Qualcomm IPQ5018

[PATCH v4 00/13] Enable USB3 for Qualcomm IPQ5018

[George Moussalem via B4 Relay]

Patch series adds Qualcomm 22ull Super-Speed USB UNIPHY driver support
present in Qualcomm IPQ5018 and IPQ5332 SoC which is required to enable
USB3. This PHY is interfaced with SNPS DWC3 USB and SNPS DWC PCIe.
Either one of the interface can use it via the mux selection present in
the TCSR register. Current patch series adds the support for UNIPHY with
DWC3 USB.

The series is now split into 3 parts:
1. Flatten USB Controller Nodes on IPQ SoCs
   link: https://lore.kernel.org/r/20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com
2. Enable USB3 for Qualcomm IPQ5018 (this patch series)
3. Enable USB3 for Qualcomm IPQ5332 (to be submitted)

---
Changes in v4:
- Reverted change to rename the binding file.
  The qcom,ipq5018-uniphy-usb3-phy compatible string is added there.
- Removed redundant #clock-cells and #phy-cells constraint
- Updated description of CONFIG symbol to reflect it is a combo
  PCIe/USB3 PHY.
- Added separate patch to remove unused of_device.h header file
- Added separate patch to drop unused phy_to_dw_phy() macro
- Left names of macro definitions unchanged.
  This can be revisited in a future patch submission if deemed necessary
- Inlined reset_control_bulk_assert instead of using a single-use goto
  as suggested by Konrad.
- Replaced regmap_set_bits with regmap_assign_bits and pass the enable
  argument directly to the function.
- It's worth noting that I left the logic to register 1 phy in this
  patch unchanged despite Konard's suggestion to register both
  (PCIe and USB3) to avoid changing the existing binding for the
  existing PCIe phy instances in ipq5018/ipq5332. Although the silicon
  is capable of supporting both PCIe and USB3, the instances in scope
  are wired for single mode only. The next patch set will register both
  PCIe and USB3 PHYs for the combo PHY instance in IPQ5332 and use
  #phy-cells to select the right PHY in the respective PCIe and USB3
  controller nodes.
- Updated clock order of the IPQ5018 USB3 PHY node to match the order in
  the binding file.
- Corrected commit title of last patch to enable the USB3 PHY on the
  IPQ5018 RDP432-C2 board.
- Link to v3: https://lore.kernel.org/r/20260825-ipq5018-usb3-v3-0-39be0955a6aa@outlook.com

Changes in v3:
- The biggest change of this revision is that it does not create a new
  driver but instead adjust the existing qcom-uniphy-pcie-28lp driver
  for which the binding is also updated. Both the binding and the driver
  have been renamed to reflect the updated scope for both PCIe and USB3.
- The description of the qcom,phy-usb-mux-sel property has been updated
  based on Krzysztof's feedback to clarify that PCIe is the default mode
  (with absence of the property) and that the property is only used to
  select USB3 mode.
- Updated the driver using multiple patches to:
  - Rename the driver (incl. symbol) and change scope from PCIe to PCIe
    and USB3 combo PHY, existing compatible strings remain unchanged.
  - Refactor and simplify the phy initialization register/value pairs
  - Use bulk reset_control API to allow for uniform way of acquiring and
    managing resets for both legacy (unnamed resources) and new (named
    resources) to maintain backward compatibility.
  - Add support for the USB3 PHY instance on IPQ5018 SoCs.
  - Add support for the combo PCIe/USB3 PHY instance on IPQ5332 SoCs.
- Updated the compatible string of the existing PCIe PHY (instance 0)
  node in the IPQ5332 SoC devicetree to reflect it is a combo PCIe/USB3
  PHY. In addition to the existing PCIe-specific resources, added the
  clock and resets required for USB3 support. The node is now used for
  both PCIe and USB3 PHYs, and the correct PHY instance is returned
  based on the phy-cells argument.
- Added a patch to enable building the driver as a module (which was
  missing for the original driver).
- Updated Praveen's email address to praveenkumar.i@oss.qualcomm.com
  including his SoB tags and retained his authorship of the original
  patches.
- Moved patches related to flattening the USB controllers nodes to a
  separate patch series:
  link: https://lore.kernel.org/r/20260825-ipq-flatten-usb-v1-0-5c1f3170bbe9@outlook.com
- Moved patches related to enabling USB3 for Qualcomm IPQ5332 to a
  separate patch series (to be submitted).
- Link to v2: https://lore.kernel.org/r/20260812-ipq5018-usb3-v2-0-8f355d7ff0ef@outlook.com

Changes in v2:
- Rebased on top of master tree
- Included support for IPQ5018
- Changed bindings filename to match compatible string
- Dropped items from compatible list in bindings file
- Added required block in bindings file
- Removed double space of reset property in example in bindings file
- Added branching logic based on compatible string to define the right
  clocks per SoC in bindings file
- Renamed phy driver to phy-qcom-uniphy-usb-ss-22ull.c
- Added missing error handling uniphy_usb_init in phy driver
- Changed to use devm_clk_hw_register_fixed_rate to register fixed rate
  pipe clock
- Changed to use devm_of_clk_add_hw_provider to register clock provider
- Release exclusive get of vdd and changed to devm_regulator_get as the
  regulator supply is also acquired by the m31 USB2 phy driver
- Inlined acquisition of clocks to phy probe function
- Use reverse xmas tree sorting of variables in phy driver probe
- Moved USB mux selection away from phy init to probe as it needs to be
  set before the controller is taken out of reset.
- Flattened the USB controller nodes in line with latest bindings and
  flattened driver approach for both SoCs.
- Set clock frequencies in IPQ5018 controller node to ensure they're
  parented correctly and override any freqs set by the bootloader.
- Removed patch to add usb phy node for IPQ5332 as the pcie0 phy shares
  the same MMIO as the usb3 phy. Hence, chose the approach to override
  the compatible string of said node and assign the right clocks, reset,
  and related properties upon enabling it as a USB3 phy instead of
  adding a new node with the same unit and reg address space.
- Link to v1: https://lore.kernel.org/r/20230929084209.3033093-1-quic_ipkumar@quicinc.com

---
George Moussalem (13):
      dt-bindings: phy: qcom,ipq5332-uniphy-pcie: Document the IPQ5018 USB3 PHY
      phy: qualcomm: qcom-uniphy-pcie-28lp: Convert to PCIe/USB3 combo PHY driver
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Remove unused of_device.h header file
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Drop unused phy_to_dw_phy macro
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Refactor init regs table definitions
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Use bulk reset_control API
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Assert reset on clock enable failure
      phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Add support for USB3 PHY on IPQ5018
      arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node
      dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018
      arm64: dts: qcom: ipq5018: Add clocks required for USB3 support
      arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node
      arm64: dts: qcom: ipq5018-rdp432-c2: Enable USB Super-Speed PHY

 .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml |  44 +-
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml    |  21 +-
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts     |  14 +
 arch/arm64/boot/dts/qcom/ipq5018.dtsi              |  33 +-
 drivers/phy/qualcomm/Kconfig                       |  24 +-
 drivers/phy/qualcomm/Makefile                      |   2 +-
 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c   | 331 ---------------
 .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 461 +++++++++++++++++++++
 8 files changed, 574 insertions(+), 356 deletions(-)
---
base-commit: 32b6ef9a5d0eca44f9cd91f52f4faa89f145a0de
change-id: 20260803-ipq5018-usb3-4b289b1ed16e
prerequisite-message-id: <20260906-ipq-flatten-usb-v3-0-13e4e0f63123@outlook.com>
prerequisite-patch-id: dd37852a0fd8928e6dd6d66e62c06d7d8f5d38d0
prerequisite-patch-id: 60972378af51aa5a2797a0ff0e62214e7dd243fe
prerequisite-patch-id: 5b791e87c7884503287a8a536958d89eb1969f80
prerequisite-patch-id: 95483f0c1984a0c16902b52b7b26793c38f466fe
prerequisite-patch-id: 51b5158ae634dd1c0713d77b0bb9473b4c88985e
prerequisite-patch-id: 5bf2892e76e4c1d3fd4e93f093c8169e23e0908d
prerequisite-patch-id: bb7b127468635b641c24555cd2e81fa201087ecd
prerequisite-patch-id: 6668bf3110dc6f763084c0c5d65833a85301bf44
prerequisite-patch-id: b7ebb4aec1ea4e78b2d498018b1413aaa056555b
prerequisite-patch-id: eeb34fd04ec7c02da54b06f4730a9b2bb75a71e8

Best regards,
-- 
George Moussalem <george.moussalem@outlook.com>

[PATCH v4 01/13] dt-bindings: phy: qcom,ipq5332-uniphy-pcie: Document the IPQ5018 USB3 PHY

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Describe the USB3 PHY found in the IPQ5018 SoC, so add the compatible
string for it as well as the required resources (clocks and resets).

The PCIe and USB physical pads are muxed and selection is done via a
control register in TCSR. By default, PCIe mode is selected, hence make
the property for USB mux selection required.

In addition, the PHY requires a 5V supply for USB3 mode operation.

Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 44 ++++++++++++++++++++--
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
index 6e9df81441e9..f59fa4e88866 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm UNIPHY PCIe 28LP PHY
+title: Qualcomm UNIPHY PCIe and USB3 28LP PHY
 
 maintainers:
   - Nitheesh Sekar <quic_nsekar@quicinc.com>
@@ -17,6 +17,7 @@ properties:
   compatible:
     enum:
       - qcom,ipq5018-uniphy-pcie-phy
+      - qcom,ipq5018-uniphy-usb3-phy
       - qcom,ipq5332-uniphy-pcie-phy
 
   reg:
@@ -27,9 +28,24 @@ properties:
     maxItems: 2
 
   resets:
-    minItems: 2
+    minItems: 1
     maxItems: 3
 
+  vdd-supply:
+    description:
+      Phandle to 5V regulator supply to PHY digital circuit.
+
+  qcom,phy-usb-mux-sel:
+    description:
+      TCSR register address for mux selection control for PCIe / USB3 mode.
+      If the property is set, the driver will configure USB3 mux selection.
+      If not set, the setting defaults to PCIe mux selection (BIT(0) = 0).
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      - items:
+          - description: phandle to TCSR syscon
+          - description: offset of PHY mux selection register
+
   "#phy-cells":
     const: 0
 
@@ -47,7 +63,6 @@ required:
   - resets
   - "#phy-cells"
   - "#clock-cells"
-  - num-lanes
 
 additionalProperties: false
 
@@ -67,6 +82,27 @@ allOf:
           items:
             - description: phy reset
             - description: cfg reset
+      required:
+        - num-lanes
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-uniphy-usb3-phy
+    then:
+      properties:
+        clocks:
+          items:
+            - description: usb3 pipe clock
+            - description: usb3 cfg ahb clock
+        resets:
+          items:
+            - description: usb3 phy reset
+      required:
+        - vdd-supply
+        - qcom,phy-usb-mux-sel
 
   - if:
       properties:
@@ -85,6 +121,8 @@ allOf:
             - description: phy reset
             - description: ahb reset
             - description: cfg reset
+      required:
+        - num-lanes
 
 examples:
   - |

-- 
2.53.0

[PATCH v4 02/13] phy: qualcomm: qcom-uniphy-pcie-28lp: Convert to PCIe/USB3 combo PHY driver

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

This PHY found in IPQ5332 and IPQ5018 SoCs is actually a multi-purpose
PCIe/USB3 combo PHY. The driver was initially created for PCIe PHY
support only. As such, rename the driver and generalize function and
struct names to reflect that it is a PCIe and USB3 combo PHY driver so
that USB3 support can be added in subsequent patches.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/phy/qualcomm/Kconfig                       | 24 +++----
 drivers/phy/qualcomm/Makefile                      |  2 +-
 ...cie-28lp.c => phy-qcom-uniphy-pcie-usb3-28lp.c} | 83 +++++++++++-----------
 3 files changed, 53 insertions(+), 56 deletions(-)

diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig
index d910a5d1a1ac..2db65815b297 100644
--- a/drivers/phy/qualcomm/Kconfig
+++ b/drivers/phy/qualcomm/Kconfig
@@ -155,19 +155,6 @@ config PHY_QCOM_M31_USB
 	  management. This driver is required even for peripheral only or
 	  host only mode configurations.
 
-config PHY_QCOM_UNIPHY_PCIE_28LP
-	bool "PCIE UNIPHY 28LP PHY driver"
-	depends on ARCH_QCOM
-	depends on COMMON_CLK
-	depends on HAS_IOMEM
-	depends on OF
-	select GENERIC_PHY
-	help
-	  Enable this to support the PCIe UNIPHY 28LP phy transceiver that
-	  is used with PCIe controllers on Qualcomm IPQ5332 chips. It
-	  handles PHY initialization, clock management required after
-	  resetting the hardware and power management.
-
 config PHY_QCOM_M31_EUSB
 	tristate "Qualcomm M31 eUSB2 PHY driver support"
 	depends on USB && (ARCH_QCOM || COMPILE_TEST)
@@ -178,6 +165,17 @@ config PHY_QCOM_M31_EUSB
 	  up of the associated USB repeater that is paired with the eUSB2
 	  PHY.
 
+config PHY_QCOM_UNIPHY_PCIE_USB3_28LP
+	bool "Qualcomm IPQ5332 UNIPHY PCIe USB3 28LP PHY driver"
+	depends on OF && (ARCH_QCOM || COMPILE_TEST)
+	select GENERIC_PHY
+	select MFD_SYSCON
+	help
+	  Enable this to support the Qualcomm multi-purpose PCIe/USB3 UNIPHY
+	  transceiver that is used on Qualcomm IPQ5018 and IPQ5332 SoCs with
+	  PCIe and USB controllers. It handles PHY initialization, clock
+	  management required after resetting the hardware and power management.
+
 config PHY_QCOM_USB_HS
 	tristate "Qualcomm USB HS PHY module"
 	depends on USB_ULPI_BUS
diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile
index 8bf887d58ee4..6e2e9737e387 100644
--- a/drivers/phy/qualcomm/Makefile
+++ b/drivers/phy/qualcomm/Makefile
@@ -18,7 +18,7 @@ obj-$(CONFIG_PHY_QCOM_QMP_USB_LEGACY)	+= phy-qcom-qmp-usb-legacy.o
 
 obj-$(CONFIG_PHY_QCOM_QUSB2)		+= phy-qcom-qusb2.o
 obj-$(CONFIG_PHY_QCOM_EUSB2_REPEATER)	+= phy-qcom-eusb2-repeater.o
-obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_28LP)	+= phy-qcom-uniphy-pcie-28lp.o
+obj-$(CONFIG_PHY_QCOM_UNIPHY_PCIE_USB3_28LP)	+= phy-qcom-uniphy-pcie-usb3-28lp.o
 obj-$(CONFIG_PHY_QCOM_USB_HS) 		+= phy-qcom-usb-hs.o
 obj-$(CONFIG_PHY_QCOM_USB_HSIC) 	+= phy-qcom-usb-hsic.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM)	+= phy-qcom-usb-hs-28nm.o
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
similarity index 76%
rename from drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
rename to drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index 324c0a5d658e..53512db90eb3 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -43,29 +43,29 @@
 #define PHY_CFG_EIOS_DTCT_REG			0x3e4
 #define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME		0x3e8
 
-enum qcom_uniphy_pcie_type {
+enum qcom_uniphy_type {
 	PHY_TYPE_PCIE = 1,
 	PHY_TYPE_PCIE_GEN2,
 	PHY_TYPE_PCIE_GEN3,
 };
 
-struct qcom_uniphy_pcie_regs {
+struct qcom_uniphy_regs {
 	u32 offset;
 	u32 val;
 };
 
-struct qcom_uniphy_pcie_data {
+struct qcom_uniphy_data {
 	int lane_offset; /* offset between the lane register bases */
 	u32 phy_type;
-	const struct qcom_uniphy_pcie_regs *init_seq;
+	const struct qcom_uniphy_regs *init_seq;
 	u32 init_seq_num;
 	u32 pipe_clk_rate;
 };
 
-struct qcom_uniphy_pcie {
+struct qcom_uniphy {
 	struct phy phy;
 	struct device *dev;
-	const struct qcom_uniphy_pcie_data *data;
+	const struct qcom_uniphy_data *data;
 	struct clk_bulk_data *clks;
 	int num_clks;
 	struct reset_control *resets;
@@ -73,9 +73,9 @@ struct qcom_uniphy_pcie {
 	int lanes;
 };
 
-#define phy_to_dw_phy(x)	container_of((x), struct qca_uni_pcie_phy, phy)
+#define phy_to_dw_phy(x)	container_of((x), struct qcom_uniphy, phy)
 
-static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
+static const struct qcom_uniphy_regs ipq5018_pcie_regs[] = {
 	{
 		.offset = SSCG_CTRL_REG_4,
 		.val = 0x1cb9,
@@ -109,7 +109,7 @@ static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
 	},
 };
 
-static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
+static const struct qcom_uniphy_regs ipq5332_pcie_regs[] = {
 	{
 		.offset = PHY_CFG_PLLCFG,
 		.val = 0x30,
@@ -122,26 +122,26 @@ static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
 	},
 };
 
-static const struct qcom_uniphy_pcie_data ipq5018_data = {
+static const struct qcom_uniphy_data ipq5018_pcie_data = {
 	.lane_offset	= 0x800,
 	.phy_type	= PHY_TYPE_PCIE_GEN2,
-	.init_seq	= ipq5018_regs,
-	.init_seq_num	= ARRAY_SIZE(ipq5018_regs),
+	.init_seq	= ipq5018_pcie_regs,
+	.init_seq_num	= ARRAY_SIZE(ipq5018_pcie_regs),
 	.pipe_clk_rate	= 125 * MEGA,
 };
 
-static const struct qcom_uniphy_pcie_data ipq5332_data = {
+static const struct qcom_uniphy_data ipq5332_pcie_data = {
 	.lane_offset	= 0x800,
 	.phy_type	= PHY_TYPE_PCIE_GEN3,
-	.init_seq	= ipq5332_regs,
-	.init_seq_num	= ARRAY_SIZE(ipq5332_regs),
+	.init_seq	= ipq5332_pcie_regs,
+	.init_seq_num	= ARRAY_SIZE(ipq5332_pcie_regs),
 	.pipe_clk_rate	= 250 * MEGA,
 };
 
-static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
+static void qcom_uniphy_pcie_usb3_init(struct qcom_uniphy *phy)
 {
-	const struct qcom_uniphy_pcie_data *data = phy->data;
-	const struct qcom_uniphy_pcie_regs *init_seq;
+	const struct qcom_uniphy_data *data = phy->data;
+	const struct qcom_uniphy_regs *init_seq;
 	void __iomem *base = phy->base;
 	int lane, i;
 
@@ -157,7 +157,7 @@ static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy)
 
 static int qcom_uniphy_pcie_power_off(struct phy *x)
 {
-	struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+	struct qcom_uniphy *phy = phy_get_drvdata(x);
 
 	clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
 
@@ -166,7 +166,7 @@ static int qcom_uniphy_pcie_power_off(struct phy *x)
 
 static int qcom_uniphy_pcie_power_on(struct phy *x)
 {
-	struct qcom_uniphy_pcie *phy = phy_get_drvdata(x);
+	struct qcom_uniphy *phy = phy_get_drvdata(x);
 	int ret;
 
 	ret = reset_control_assert(phy->resets);
@@ -193,13 +193,13 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 
 	usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
 
-	qcom_uniphy_pcie_init(phy);
+	qcom_uniphy_pcie_usb3_init(phy);
 
 	return 0;
 }
 
-static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
-						 struct qcom_uniphy_pcie *phy)
+static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_device *pdev,
+						      struct qcom_uniphy *phy)
 {
 	struct resource *res;
 
@@ -236,9 +236,9 @@ static inline int qcom_uniphy_pcie_get_resources(struct platform_device *pdev,
  *    clk  |   +-------+   |                   +-----+
  *         +---------------+
  */
-static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
+static inline int phy_pipe_clk_register(struct qcom_uniphy *phy, int id)
 {
-	const struct qcom_uniphy_pcie_data *data = phy->data;
+	const struct qcom_uniphy_data *data = phy->data;
 	struct clk_hw *hw;
 	char name[64];
 
@@ -252,30 +252,29 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, int id)
 	return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
 }
 
-static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
+static const struct of_device_id qcom_uniphy_pcie_usb3_id_table[] = {
 	{
 		.compatible = "qcom,ipq5018-uniphy-pcie-phy",
-		.data = &ipq5018_data,
+		.data = &ipq5018_pcie_data,
 	}, {
 		.compatible = "qcom,ipq5332-uniphy-pcie-phy",
-		.data = &ipq5332_data,
-	}, {
-		/* Sentinel */
+		.data = &ipq5332_pcie_data,
 	},
+	{ },
 };
-MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table);
+MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_usb3_id_table);
 
-static const struct phy_ops pcie_ops = {
+static const struct phy_ops qcom_uniphy_pcie_ops = {
 	.power_on	= qcom_uniphy_pcie_power_on,
 	.power_off	= qcom_uniphy_pcie_power_off,
 	.owner          = THIS_MODULE,
 };
 
-static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
+static int qcom_uniphy_pcie_usb3_probe(struct platform_device *pdev)
 {
 	struct phy_provider *phy_provider;
 	struct device *dev = &pdev->dev;
-	struct qcom_uniphy_pcie *phy;
+	struct qcom_uniphy *phy;
 	struct phy *generic_phy;
 	int ret;
 
@@ -294,12 +293,12 @@ static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
 	if (ret)
 		return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");
 
-	ret = qcom_uniphy_pcie_get_resources(pdev, phy);
+	ret = qcom_uniphy_pcie_usb3_get_resources(pdev, phy);
 	if (ret < 0)
 		return dev_err_probe(&pdev->dev, ret,
 				     "failed to get resources: %d\n", ret);
 
-	generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);
+	generic_phy = devm_phy_create(phy->dev, NULL, &qcom_uniphy_pcie_ops);
 	if (IS_ERR(generic_phy))
 		return PTR_ERR(generic_phy);
 
@@ -317,15 +316,15 @@ static int qcom_uniphy_pcie_probe(struct platform_device *pdev)
 	return 0;
 }
 
-static struct platform_driver qcom_uniphy_pcie_driver = {
-	.probe		= qcom_uniphy_pcie_probe,
+static struct platform_driver qcom_uniphy_pcie_usb3_driver = {
+	.probe		= qcom_uniphy_pcie_usb3_probe,
 	.driver		= {
-		.name	= "qcom-uniphy-pcie",
-		.of_match_table = qcom_uniphy_pcie_id_table,
+		.name	= "qcom-uniphy-pcie-usb3-28lp",
+		.of_match_table = qcom_uniphy_pcie_usb3_id_table,
 	},
 };
 
-module_platform_driver(qcom_uniphy_pcie_driver);
+module_platform_driver(qcom_uniphy_pcie_usb3_driver);
 
-MODULE_DESCRIPTION("PCIE QCOM UNIPHY driver");
+MODULE_DESCRIPTION("Qualcomm IPQ5332 UNIPHY PCIe USB3 28LP PHY driver");
 MODULE_LICENSE("GPL");

-- 
2.53.0

Re: [PATCH v4 02/13] phy: qualcomm: qcom-uniphy-pcie-28lp: Convert to PCIe/USB3 combo PHY driver

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:40:55PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> This PHY found in IPQ5332 and IPQ5018 SoCs is actually a multi-purpose
> PCIe/USB3 combo PHY. The driver was initially created for PCIe PHY
> support only. As such, rename the driver and generalize function and
> struct names to reflect that it is a PCIe and USB3 combo PHY driver so
> that USB3 support can be added in subsequent patches.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 03/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Remove unused of_device.h header file

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Drop the unused of_device.h header file as the of_device_get_match_data
declaration was moved to of.h in below commit:
commit 82174a0a9c5c ("of: Move of_device_get_match_data() declaration")

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index 53512db90eb3..b9ca6c1c177b 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -10,7 +10,6 @@
 #include <linux/io.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
-#include <linux/of_device.h>
 #include <linux/of.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>

-- 
2.53.0

Re: [PATCH v4 03/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Remove unused of_device.h header file

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:40:56PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Drop the unused of_device.h header file as the of_device_get_match_data
> declaration was moved to of.h in below commit:
> commit 82174a0a9c5c ("of: Move of_device_get_match_data() declaration")
> 
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 04/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Drop unused phy_to_dw_phy macro

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Remove the unused phy_to_dw_phy() helper macro which is not referenced
anywhere in the driver.

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index b9ca6c1c177b..0256183fbcbd 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -72,8 +72,6 @@ struct qcom_uniphy {
 	int lanes;
 };
 
-#define phy_to_dw_phy(x)	container_of((x), struct qcom_uniphy, phy)
-
 static const struct qcom_uniphy_regs ipq5018_pcie_regs[] = {
 	{
 		.offset = SSCG_CTRL_REG_4,

-- 
2.53.0

Re: [PATCH v4 04/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Drop unused phy_to_dw_phy macro

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:40:57PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Remove the unused phy_to_dw_phy() helper macro which is not referenced
> anywhere in the driver.
> 
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 05/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Refactor init regs table definitions

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Refactor the IPQ5018/IPQ5332 UNIPHY PCIe init data by introducing a
helper macro for register/value entries and converting open-coded struct
initializers to the compact form.

No functional change intended.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 60 +++++++---------------
 1 file changed, 19 insertions(+), 41 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index 0256183fbcbd..c12de5549652 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -72,51 +72,29 @@ struct qcom_uniphy {
 	int lanes;
 };
 
+#define PHY_INIT_CFG(o, v)		\
+	{				\
+		.offset = o,		\
+		.val = v,		\
+	}
+
 static const struct qcom_uniphy_regs ipq5018_pcie_regs[] = {
-	{
-		.offset = SSCG_CTRL_REG_4,
-		.val = 0x1cb9,
-	}, {
-		.offset = SSCG_CTRL_REG_5,
-		.val = 0x023a,
-	}, {
-		.offset = SSCG_CTRL_REG_3,
-		.val = 0xd360,
-	}, {
-		.offset = SSCG_CTRL_REG_1,
-		.val = 0x1,
-	}, {
-		.offset = SSCG_CTRL_REG_2,
-		.val = 0xeb,
-	}, {
-		.offset = CDR_CTRL_REG_4,
-		.val = 0x3f9,
-	}, {
-		.offset = CDR_CTRL_REG_5,
-		.val = 0x1c9,
-	}, {
-		.offset = CDR_CTRL_REG_2,
-		.val = 0x419,
-	}, {
-		.offset = CDR_CTRL_REG_1,
-		.val = 0x200,
-	}, {
-		.offset = PCS_INTERNAL_CONTROL_2,
-		.val = 0xf101,
-	},
+	PHY_INIT_CFG(SSCG_CTRL_REG_4, 0x1cb9),
+	PHY_INIT_CFG(SSCG_CTRL_REG_5, 0x023a),
+	PHY_INIT_CFG(SSCG_CTRL_REG_3, 0xd360),
+	PHY_INIT_CFG(SSCG_CTRL_REG_1, 0x1),
+	PHY_INIT_CFG(SSCG_CTRL_REG_2, 0xeb),
+	PHY_INIT_CFG(CDR_CTRL_REG_4, 0x3f9),
+	PHY_INIT_CFG(CDR_CTRL_REG_5, 0x1c9),
+	PHY_INIT_CFG(CDR_CTRL_REG_2, 0x419),
+	PHY_INIT_CFG(CDR_CTRL_REG_1, 0x200),
+	PHY_INIT_CFG(PCS_INTERNAL_CONTROL_2, 0xf101),
 };
 
 static const struct qcom_uniphy_regs ipq5332_pcie_regs[] = {
-	{
-		.offset = PHY_CFG_PLLCFG,
-		.val = 0x30,
-	}, {
-		.offset = PHY_CFG_EIOS_DTCT_REG,
-		.val = 0x53ef,
-	}, {
-		.offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME,
-		.val = 0xcf,
-	},
+	PHY_INIT_CFG(PHY_CFG_PLLCFG, 0x30),
+	PHY_INIT_CFG(PHY_CFG_EIOS_DTCT_REG, 0x53ef),
+	PHY_INIT_CFG(PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, 0xcf),
 };
 
 static const struct qcom_uniphy_data ipq5018_pcie_data = {

-- 
2.53.0

Re: [PATCH v4 05/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Refactor init regs table definitions

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:40:58PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Refactor the IPQ5018/IPQ5332 UNIPHY PCIe init data by introducing a
> helper macro for register/value entries and converting open-coded struct
> initializers to the compact form.
> 
> No functional change intended.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 06/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Use bulk reset_control API

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Switch to using bulk reset_control functions to prepare the driver for
managing multiple resets, acquiring reset controls by name, and
uniformly storing resets in the private data structure to enable support
for future combo PHY functionality requiring multiple resets.

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 31 ++++++++++++++++------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index c12de5549652..0a50eb44c0ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -67,7 +67,8 @@ struct qcom_uniphy {
 	const struct qcom_uniphy_data *data;
 	struct clk_bulk_data *clks;
 	int num_clks;
-	struct reset_control *resets;
+	struct reset_control_bulk_data *resets;
+	int num_resets;
 	void __iomem *base;
 	int lanes;
 };
@@ -136,7 +137,7 @@ static int qcom_uniphy_pcie_power_off(struct phy *x)
 
 	clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
 
-	return reset_control_assert(phy->resets);
+	return reset_control_bulk_assert(phy->num_resets, phy->resets);
 }
 
 static int qcom_uniphy_pcie_power_on(struct phy *x)
@@ -144,7 +145,7 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 	struct qcom_uniphy *phy = phy_get_drvdata(x);
 	int ret;
 
-	ret = reset_control_assert(phy->resets);
+	ret = reset_control_bulk_assert(phy->num_resets, phy->resets);
 	if (ret) {
 		dev_err(phy->dev, "reset assert failed (%d)\n", ret);
 		return ret;
@@ -152,7 +153,7 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 
 	usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
 
-	ret = reset_control_deassert(phy->resets);
+	ret = reset_control_bulk_deassert(phy->num_resets, phy->resets);
 	if (ret) {
 		dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
 		return ret;
@@ -176,19 +177,33 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_device *pdev,
 						      struct qcom_uniphy *phy)
 {
+	struct device *dev = phy->dev;
 	struct resource *res;
+	int i, count, ret;
 
 	phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 	if (IS_ERR(phy->base))
 		return PTR_ERR(phy->base);
 
-	phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);
+	phy->num_clks = devm_clk_bulk_get_all(dev, &phy->clks);
 	if (phy->num_clks < 0)
 		return phy->num_clks;
 
-	phy->resets = devm_reset_control_array_get_exclusive(phy->dev);
-	if (IS_ERR(phy->resets))
-		return PTR_ERR(phy->resets);
+	count = of_count_phandle_with_args(dev->of_node, "resets", "#reset-cells");
+	if (count < 0)
+		return count;
+
+	phy->resets = devm_kcalloc(dev, count, sizeof(*phy->resets), GFP_KERNEL);
+	if (!phy->resets)
+		return -ENOMEM;
+
+	for (i = 0; i < count; i++) {
+		phy->resets[i].rstc = devm_reset_control_get_exclusive_by_index(dev, i);
+		if (IS_ERR(phy->resets[i].rstc))
+			return PTR_ERR(phy->resets[i].rstc);
+	}
+
+	phy->num_resets = count;
 
 	return 0;
 }

-- 
2.53.0

[PATCH v4 07/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Assert reset on clock enable failure

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

When the PHY fails the enable clocks, it leaves the PHY out of reset.
Fix this by asserting the reset before returning the error.

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index 0a50eb44c0ce..15b17044fde3 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -164,6 +164,7 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 	ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
 	if (ret) {
 		dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
+		reset_control_bulk_assert(phy->num_resets, phy->resets);
 		return ret;
 	}
 

-- 
2.53.0

Re: [PATCH v4 07/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Assert reset on clock enable failure

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:41:00PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> When the PHY fails the enable clocks, it leaves the PHY out of reset.
> Fix this by asserting the reset before returning the error.
> 
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 08/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Add support for USB3 PHY on IPQ5018

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add support for the USB3 PHY on IPQ5018 chipsets.

The PHY outputs a 250MHz PIPE clock routed to and gated by the GCC, so
register a fixed rate clock. In addition, add the register/value pairs
for the PHY initialization sequence.

The code to acquire clocks and resets is the same as for PCIe so no
changes are needed. Add a USB3-specific helper function to acquire the
required regulator and TCSR syscon for USB mux selection. The PCIe and
USB3 pads are muxed so select USB3 mode in TCSR which needs to occur
before the DWC3 USB3 controller resets. Otherwise, the SS link doesn't
train and remains stuck in RX.Detect.

Add PHY ops for USB3 power on/off sequences to account for USB3-specific
delay timings and enabling/disabling the PHY supply.

Rename the existing reset delay timings to describe they are for PCIe.
Lastly, add the USB3 PHY type to the UNIPHY PHY type enum and remove the
GEN2 and GEN3 PCIe types as the driver makes no distinction between the
two which also makes it easier to distinguish between the PCIe and USB3
PHYs.

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 178 ++++++++++++++++++---
 1 file changed, 159 insertions(+), 19 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
index 15b17044fde3..810121508634 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c
@@ -14,15 +14,22 @@
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
 #include <linux/reset.h>
 #include <linux/units.h>
 
-#define RST_ASSERT_DELAY_MIN_US		100
-#define RST_ASSERT_DELAY_MAX_US		150
-#define PIPE_CLK_DELAY_MIN_US		5000
-#define PIPE_CLK_DELAY_MAX_US		5100
-#define CLK_EN_DELAY_MIN_US		30
-#define CLK_EN_DELAY_MAX_US		50
+#define PCIE_RST_ASSERT_DELAY_MIN_US	100
+#define PCIE_RST_ASSERT_DELAY_MAX_US	150
+#define PCIE_PIPE_CLK_DELAY_MIN_US	5000
+#define PCIE_PIPE_CLK_DELAY_MAX_US	5100
+#define PCIE_CLK_EN_DELAY_MIN_US	30
+#define PCIE_CLK_EN_DELAY_MAX_US	50
+
+#define USB3_RST_ASSERT_DELAY_MIN_US	1
+#define USB3_RST_ASSERT_DELAY_MAX_US	5
+#define USB3_CLK_EN_DELAY_MIN_US	35
+#define USB3_CLK_EN_DELAY_MAX_US	40
+
 #define CDR_CTRL_REG_1		0x80
 #define CDR_CTRL_REG_2		0x84
 #define CDR_CTRL_REG_3		0x88
@@ -42,10 +49,13 @@
 #define PHY_CFG_EIOS_DTCT_REG			0x3e4
 #define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME		0x3e8
 
+#define TCSR_USB_MUX_SEL		BIT(0)
+
+#define PHY_IS_USB3(phy)	((phy)->data->phy_type == PHY_TYPE_USB3)
+
 enum qcom_uniphy_type {
 	PHY_TYPE_PCIE = 1,
-	PHY_TYPE_PCIE_GEN2,
-	PHY_TYPE_PCIE_GEN3,
+	PHY_TYPE_USB3,
 };
 
 struct qcom_uniphy_regs {
@@ -71,6 +81,9 @@ struct qcom_uniphy {
 	int num_resets;
 	void __iomem *base;
 	int lanes;
+	struct regulator *vreg;
+	struct regmap *tcsr;
+	unsigned int mux_offset;
 };
 
 #define PHY_INIT_CFG(o, v)		\
@@ -92,6 +105,14 @@ static const struct qcom_uniphy_regs ipq5018_pcie_regs[] = {
 	PHY_INIT_CFG(PCS_INTERNAL_CONTROL_2, 0xf101),
 };
 
+static const struct qcom_uniphy_regs ipq5018_usb3_regs[] = {
+	PHY_INIT_CFG(SSCG_CTRL_REG_4, 0x1cb9),
+	PHY_INIT_CFG(SSCG_CTRL_REG_5, 0x023a),
+	PHY_INIT_CFG(SSCG_CTRL_REG_3, 0xd360),
+	PHY_INIT_CFG(SSCG_CTRL_REG_1, 0x1),
+	PHY_INIT_CFG(SSCG_CTRL_REG_2, 0xeb),
+};
+
 static const struct qcom_uniphy_regs ipq5332_pcie_regs[] = {
 	PHY_INIT_CFG(PHY_CFG_PLLCFG, 0x30),
 	PHY_INIT_CFG(PHY_CFG_EIOS_DTCT_REG, 0x53ef),
@@ -100,15 +121,23 @@ static const struct qcom_uniphy_regs ipq5332_pcie_regs[] = {
 
 static const struct qcom_uniphy_data ipq5018_pcie_data = {
 	.lane_offset	= 0x800,
-	.phy_type	= PHY_TYPE_PCIE_GEN2,
+	.phy_type	= PHY_TYPE_PCIE,
 	.init_seq	= ipq5018_pcie_regs,
 	.init_seq_num	= ARRAY_SIZE(ipq5018_pcie_regs),
 	.pipe_clk_rate	= 125 * MEGA,
 };
 
+static const struct qcom_uniphy_data ipq5018_usb3_data = {
+	.lane_offset	= 0x800,
+	.phy_type	= PHY_TYPE_USB3,
+	.init_seq	= ipq5018_usb3_regs,
+	.init_seq_num	= ARRAY_SIZE(ipq5018_usb3_regs),
+	.pipe_clk_rate	= 250 * MEGA,
+};
+
 static const struct qcom_uniphy_data ipq5332_pcie_data = {
 	.lane_offset	= 0x800,
-	.phy_type	= PHY_TYPE_PCIE_GEN3,
+	.phy_type	= PHY_TYPE_PCIE,
 	.init_seq	= ipq5332_pcie_regs,
 	.init_seq_num	= ARRAY_SIZE(ipq5332_pcie_regs),
 	.pipe_clk_rate	= 250 * MEGA,
@@ -151,7 +180,7 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 		return ret;
 	}
 
-	usleep_range(RST_ASSERT_DELAY_MIN_US, RST_ASSERT_DELAY_MAX_US);
+	usleep_range(PCIE_RST_ASSERT_DELAY_MIN_US, PCIE_RST_ASSERT_DELAY_MAX_US);
 
 	ret = reset_control_bulk_deassert(phy->num_resets, phy->resets);
 	if (ret) {
@@ -159,7 +188,7 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 		return ret;
 	}
 
-	usleep_range(PIPE_CLK_DELAY_MIN_US, PIPE_CLK_DELAY_MAX_US);
+	usleep_range(PCIE_PIPE_CLK_DELAY_MIN_US, PCIE_PIPE_CLK_DELAY_MAX_US);
 
 	ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
 	if (ret) {
@@ -168,13 +197,90 @@ static int qcom_uniphy_pcie_power_on(struct phy *x)
 		return ret;
 	}
 
-	usleep_range(CLK_EN_DELAY_MIN_US, CLK_EN_DELAY_MAX_US);
+	usleep_range(PCIE_CLK_EN_DELAY_MIN_US, PCIE_CLK_EN_DELAY_MAX_US);
 
 	qcom_uniphy_pcie_usb3_init(phy);
 
 	return 0;
 }
 
+static int qcom_uniphy_usb3_power_off(struct phy *x)
+{
+	struct qcom_uniphy *phy = phy_get_drvdata(x);
+
+	clk_bulk_disable_unprepare(phy->num_clks, phy->clks);
+
+	reset_control_bulk_assert(phy->num_resets, phy->resets);
+
+	regulator_disable(phy->vreg);
+
+	return 0;
+}
+
+static int qcom_uniphy_usb3_power_on(struct phy *x)
+{
+	struct qcom_uniphy *phy = phy_get_drvdata(x);
+	int ret;
+
+	ret = regulator_enable(phy->vreg);
+	if (ret) {
+		dev_err(phy->dev, "failed to enable regulator: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_control_bulk_assert(phy->num_resets, phy->resets);
+	if (ret) {
+		dev_err(phy->dev, "reset assert failed (%d)\n", ret);
+		goto err_disable_regulator;
+	}
+
+	usleep_range(USB3_RST_ASSERT_DELAY_MIN_US, USB3_RST_ASSERT_DELAY_MAX_US);
+
+	ret = reset_control_bulk_deassert(phy->num_resets, phy->resets);
+	if (ret) {
+		dev_err(phy->dev, "reset deassert failed (%d)\n", ret);
+		goto err_disable_regulator;
+	}
+
+	ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);
+	if (ret) {
+		dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);
+		reset_control_bulk_assert(phy->num_resets, phy->resets);
+		goto err_disable_regulator;
+	}
+
+	usleep_range(USB3_CLK_EN_DELAY_MIN_US, USB3_CLK_EN_DELAY_MAX_US);
+
+	qcom_uniphy_pcie_usb3_init(phy);
+
+	return 0;
+
+err_disable_regulator:
+	regulator_disable(phy->vreg);
+
+	return ret;
+}
+
+static inline int qcom_uniphy_usb3_get_resources(struct platform_device *pdev,
+						 struct qcom_uniphy *phy)
+{
+	struct device *dev = phy->dev;
+
+	phy->vreg = devm_regulator_get(dev, "vdd");
+	if (IS_ERR(phy->vreg))
+		return dev_err_probe(dev, PTR_ERR(phy->vreg), "failed to get regulator\n");
+
+	phy->tcsr = syscon_regmap_lookup_by_phandle_args(dev->of_node,
+							 "qcom,phy-usb-mux-sel",
+							 1, &phy->mux_offset);
+	if (IS_ERR(phy->tcsr))
+		return dev_err_probe(dev, PTR_ERR(phy->tcsr), "failed to get regmap\n");
+
+	phy->lanes = 1;
+
+	return 0;
+}
+
 static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_device *pdev,
 						      struct qcom_uniphy *phy)
 {
@@ -206,6 +312,13 @@ static inline int qcom_uniphy_pcie_usb3_get_resources(struct platform_device *pd
 
 	phy->num_resets = count;
 
+	if (PHY_IS_USB3(phy))
+		return qcom_uniphy_usb3_get_resources(pdev, phy);
+
+	ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes);
+	if (ret)
+		return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");
+
 	return 0;
 }
 
@@ -233,7 +346,8 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy *phy, int id)
 	struct clk_hw *hw;
 	char name[64];
 
-	snprintf(name, sizeof(name), "phy%d_pipe_clk_src", id);
+	snprintf(name, sizeof(name), "%sphy%d_pipe_clk_src",
+		 (PHY_IS_USB3(phy)) ? "usb" : "", id);
 	hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,
 					     data->pipe_clk_rate);
 	if (IS_ERR(hw))
@@ -243,10 +357,19 @@ static inline int phy_pipe_clk_register(struct qcom_uniphy *phy, int id)
 	return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);
 }
 
+static int qcom_uniphy_usb_mux_select(struct qcom_uniphy *phy, bool enable)
+{
+	return regmap_assign_bits(phy->tcsr, phy->mux_offset,
+				  TCSR_USB_MUX_SEL, enable);
+}
+
 static const struct of_device_id qcom_uniphy_pcie_usb3_id_table[] = {
 	{
 		.compatible = "qcom,ipq5018-uniphy-pcie-phy",
 		.data = &ipq5018_pcie_data,
+	}, {
+		.compatible = "qcom,ipq5018-uniphy-usb3-phy",
+		.data = &ipq5018_usb3_data,
 	}, {
 		.compatible = "qcom,ipq5332-uniphy-pcie-phy",
 		.data = &ipq5332_pcie_data,
@@ -261,6 +384,12 @@ static const struct phy_ops qcom_uniphy_pcie_ops = {
 	.owner          = THIS_MODULE,
 };
 
+static const struct phy_ops qcom_uniphy_usb3_ops = {
+	.power_on	= qcom_uniphy_usb3_power_on,
+	.power_off	= qcom_uniphy_usb3_power_off,
+	.owner          = THIS_MODULE,
+};
+
 static int qcom_uniphy_pcie_usb3_probe(struct platform_device *pdev)
 {
 	struct phy_provider *phy_provider;
@@ -280,16 +409,15 @@ static int qcom_uniphy_pcie_usb3_probe(struct platform_device *pdev)
 	if (!phy->data)
 		return -EINVAL;
 
-	ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes);
-	if (ret)
-		return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");
-
 	ret = qcom_uniphy_pcie_usb3_get_resources(pdev, phy);
 	if (ret < 0)
 		return dev_err_probe(&pdev->dev, ret,
 				     "failed to get resources: %d\n", ret);
 
-	generic_phy = devm_phy_create(phy->dev, NULL, &qcom_uniphy_pcie_ops);
+	if (PHY_IS_USB3(phy))
+		generic_phy = devm_phy_create(phy->dev, NULL, &qcom_uniphy_usb3_ops);
+	else
+		generic_phy = devm_phy_create(phy->dev, NULL, &qcom_uniphy_pcie_ops);
 	if (IS_ERR(generic_phy))
 		return PTR_ERR(generic_phy);
 
@@ -304,6 +432,18 @@ static int qcom_uniphy_pcie_usb3_probe(struct platform_device *pdev)
 	if (IS_ERR(phy_provider))
 		return PTR_ERR(phy_provider);
 
+	/*
+	 * Select USB mux before the controller comes out of reset. Selecting it
+	 * later in .power_on leaves the SuperSpeed pads muxed away while the
+	 * controller resets, and the SS link training remains in Rx.Detect
+	 */
+	if (PHY_IS_USB3(phy)) {
+		ret = qcom_uniphy_usb_mux_select(phy, true);
+		if (ret)
+			return dev_err_probe(&pdev->dev, ret,
+					     "failed to select usb mux\n");
+	}
+
 	return 0;
 }
 

-- 
2.53.0

Re: [PATCH v4 08/13] phy: qualcomm: qcom-uniphy-pcie-usb3-28lp: Add support for USB3 PHY on IPQ5018

[Manivannan Sadhasivam]

On Tue, Sep 08, 2026 at 01:41:01PM +0400, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@outlook.com>
> 
> Add support for the USB3 PHY on IPQ5018 chipsets.
> 
> The PHY outputs a 250MHz PIPE clock routed to and gated by the GCC, so
> register a fixed rate clock. In addition, add the register/value pairs
> for the PHY initialization sequence.
> 
> The code to acquire clocks and resets is the same as for PCIe so no
> changes are needed. Add a USB3-specific helper function to acquire the
> required regulator and TCSR syscon for USB mux selection. The PCIe and
> USB3 pads are muxed so select USB3 mode in TCSR which needs to occur
> before the DWC3 USB3 controller resets. Otherwise, the SS link doesn't
> train and remains stuck in RX.Detect.
> 
> Add PHY ops for USB3 power on/off sequences to account for USB3-specific
> delay timings and enabling/disabling the PHY supply.
> 
> Rename the existing reset delay timings to describe they are for PCIe.
> Lastly, add the USB3 PHY type to the UNIPHY PHY type enum and remove the
> GEN2 and GEN3 PCIe types as the driver makes no distinction between the
> two which also makes it easier to distinguish between the PCIe and USB3
> PHYs.
> 
> Tested-by: Stanislaw Pal <kuncy7@gmail.com>
> Signed-off-by: George Moussalem <george.moussalem@outlook.com>

LGTM! Just one minor nit below. With that fixed,

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

> ---
>  .../phy/qualcomm/phy-qcom-uniphy-pcie-usb3-28lp.c  | 178 ++++++++++++++++++---
>  1 file changed, 159 insertions(+), 19 deletions(-)
> 

[...]

> +static inline int qcom_uniphy_usb3_get_resources(struct platform_device *pdev,
> +						 struct qcom_uniphy *phy)

Drop the 'inline' keyword please. Modern compilers will inline functions on
their own irrespective of this keyword.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

[PATCH v4 09/13] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add the USB3 PHY node and populate the USB DT clock on the GCC node for
the GCC to gate the PIPE clock supplied by the USB3 PHY.

Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 956d3217ec52..34d882b047bc 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -179,6 +179,23 @@ usbphy0: phy@5b000 {
 			status = "disabled";
 		};
 
+		usbphy1: phy@5d000 {
+			compatible = "qcom,ipq5018-uniphy-usb3-phy";
+			reg = <0x0005d000 0x800>;
+
+			clocks = <&gcc GCC_USB0_PIPE_CLK>,
+				 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+
+			resets = <&gcc GCC_USB0_PHY_BCR>;
+
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+
+			qcom,phy-usb-mux-sel = <&tcsr 0x10540>;
+
+			status = "disabled";
+		};
+
 		pcie1_phy: phy@7e000 {
 			compatible = "qcom,ipq5018-uniphy-pcie-phy";
 			reg = <0x0007e000 0x800>;
@@ -436,7 +453,7 @@ gcc: clock-controller@1800000 {
 				 <&sleep_clk>,
 				 <&pcie0_phy>,
 				 <&pcie1_phy>,
-				 <0>,
+				 <&usbphy1>,
 				 <&gephy_rx_clk>,
 				 <&gephy_tx_clk>,
 				 <0>,

-- 
2.53.0

[PATCH v4 10/13] dt-bindings: usb: qcom,snps-dwc3: Add clocks for USB3 on Qualcomm IPQ5018

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add aux and lfps clocks in Qualcomm IPQ5018. These clocks are required
only for USB Super-Speed support.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 .../devicetree/bindings/usb/qcom,snps-dwc3.yaml     | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
index ea60f7220afe..5cf10863aca2 100644
--- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml
@@ -185,6 +185,26 @@ allOf:
             - const: sleep
             - const: mock_utmi
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,ipq5018-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 6
+          maxItems: 6
+        clock-names:
+          items:
+            - const: core
+            - const: iface
+            - const: sleep
+            - const: mock_utmi
+            - const: aux
+            - const: lfps
+
   - if:
       properties:
         compatible:
@@ -286,7 +306,6 @@ allOf:
         compatible:
           contains:
             enum:
-              - qcom,ipq5018-dwc3
               - qcom,msm8994-dwc3
               - qcom,qcs404-dwc3
     then:

-- 
2.53.0

[PATCH v4 11/13] arm64: dts: qcom: ipq5018: Add clocks required for USB3 support

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add aux and lfps clocks to USB controller node for Super-Speed support.
These clocks are required for USB3 mode only and are not needed for USB2
mode.

In addition, set UTMI clock frequency to ensure it's parented correctly
and override the clock rate potentially set by the bootloader.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index 34d882b047bc..a6e337e137c8 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -604,11 +604,15 @@ usb: usb@8a00000 {
 			clocks = <&gcc GCC_USB0_MASTER_CLK>,
 				 <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
 				 <&gcc GCC_USB0_SLEEP_CLK>,
-				 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+				 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
+				 <&gcc GCC_USB0_AUX_CLK>,
+				 <&gcc GCC_USB0_LFPS_CLK>;
 			clock-names = "core",
 				      "iface",
 				      "sleep",
-				      "mock_utmi";
+				      "mock_utmi",
+				      "aux",
+				      "lfps";
 			assigned-clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
 			assigned-clock-rates = <60000000>;
 

-- 
2.53.0

[PATCH v4 12/13] arm64: dts: qcom: ipq5018: Add Super-Speed UNIPHY to USB node

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add the USB3 UNIPHY to the USB controller node for USB3 support.
In addition, switch to the pipe clock supplied by the USB3 UNIPHY
instead of the UTMI clock.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
index a6e337e137c8..8e5d45a214a5 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -627,10 +627,8 @@ usb: usb@8a00000 {
 
 			resets = <&gcc GCC_USB0_BCR>;
 
-			phys = <&usbphy0>;
-			phy-names = "usb2-phy";
-
-			qcom,select-utmi-as-pipe-clk;
+			phys = <&usbphy0>, <&usbphy1>;
+			phy-names = "usb2-phy", "usb3-phy";
 
 			tx-fifo-resize;
 			snps,is-utmi-l1-suspend;

-- 
2.53.0

[PATCH v4 13/13] arm64: dts: qcom: ipq5018-rdp432-c2: Enable USB Super-Speed PHY

[George Moussalem via B4 Relay]

From: George Moussalem <george.moussalem@outlook.com>

Add the 5V supply regulator and enable USB Super-Speed PHY support.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Stanislaw Pal <kuncy7@gmail.com>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
index 8efb2b21ed9e..ca29f271e673 100644
--- a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts
@@ -22,6 +22,14 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	regulator_fixed_5p0: regulator-s0500 {
+		compatible = "regulator-fixed";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-name = "fixed_5p0";
+		gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &blsp1_uart1 {
@@ -119,6 +127,12 @@ &usbphy0 {
 	status = "okay";
 };
 
+&usbphy1 {
+	vdd-supply = <&regulator_fixed_5p0>;
+
+	status = "okay";
+};
+
 &xo_board_clk {
 	clock-div = <4>;
 	clock-mult = <1>;

-- 
2.53.0