[PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Imre Kaloz]

The hub flips the low 128K of the CKSEG1 (attribute 0) uncached alias
per CPU slice, and the cache error vector is fetched through it.
trap_init() writes the vector through TO_UNCAC(), which is not flipped,
so only slice 0 sees it. Copy it to each secondary CPU's slot as it
comes up.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Cc: stable@vger.kernel.org
Signed-off-by: Imre Kaloz <kaloz@kernel.org>
---
 arch/mips/sgi-ip27/ip27-smp.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 62733e049570..0fef66b86959 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -7,11 +7,13 @@
  * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
  */
 #include <linux/init.h>
+#include <linux/string.h>
 #include <linux/sched.h>
 #include <linux/sched/task_stack.h>
 #include <linux/topology.h>
 #include <linux/nodemask.h>
 
+#include <asm/addrspace.h>
 #include <asm/page.h>
 #include <asm/processor.h>
 #include <asm/ptrace.h>
@@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
 	per_cpu_init();
 }
 
+static void ip27_init_secondary(void)
+{
+	/*
+	 * The hub flips the low 128K of the attribute 0 uncached alias per
+	 * CPU slice and the cache error vector is fetched through that alias,
+	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
+	 */
+	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);
+
+	ip27_init_cpu();
+}
+
 static void ip27_smp_finish(void)
 {
 	hub_rt_clock_event_init();
@@ -182,7 +196,7 @@ static void __init ip27_prepare_cpus(unsigned int max_cpus)
 const struct plat_smp_ops ip27_smp_ops = {
 	.send_ipi_single	= ip27_send_ipi_single,
 	.send_ipi_mask		= ip27_send_ipi_mask,
-	.init_secondary		= ip27_init_cpu,
+	.init_secondary		= ip27_init_secondary,
 	.smp_finish		= ip27_smp_finish,
 	.boot_secondary		= ip27_boot_secondary,
 	.smp_setup		= ip27_smp_setup,

base-commit: 24a19b953e2a3d0ea5a8c4951a0ab8f32720c907
-- 
2.47.3

Re: [PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Maciej W. Rozycki]

On Wed, 21 Oct 2026, Imre Kaloz wrote:

> diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
> index 62733e049570..0fef66b86959 100644
> --- a/arch/mips/sgi-ip27/ip27-smp.c
> +++ b/arch/mips/sgi-ip27/ip27-smp.c
> @@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
>  	per_cpu_init();
>  }
>  
> +static void ip27_init_secondary(void)
> +{
> +	/*
> +	 * The hub flips the low 128K of the attribute 0 uncached alias per
> +	 * CPU slice and the cache error vector is fetched through that alias,
> +	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
> +	 */
> +	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);

 This just copies instructions between the same physical memory locations, 
from an XKPHYS mapping to its corresponding KSEG1 mapping, i.e. the bus 
addresses are the same, so please give a more elaborate explanation how 
this is supposed to work.  I guess I'm just missing something, but that 
has to be obvious from the contribution itself, also for other people that 
may come across this change in the repo in the future.

 Also, please don't cc stable with submissions targeting mainline, fixes 
will be picked up for backporting based on the Cc: tag in the commit 
description.

  Maciej

Re: [PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Thomas Bogendoerfer]

On Thu, Oct 22, 2026 at 08:07:47PM +0100, Maciej W. Rozycki wrote:
> On Wed, 21 Oct 2026, Imre Kaloz wrote:
> 
> > diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
> > index 62733e049570..0fef66b86959 100644
> > --- a/arch/mips/sgi-ip27/ip27-smp.c
> > +++ b/arch/mips/sgi-ip27/ip27-smp.c
> > @@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
> >  	per_cpu_init();
> >  }
> >  
> > +static void ip27_init_secondary(void)
> > +{
> > +	/*
> > +	 * The hub flips the low 128K of the attribute 0 uncached alias per
> > +	 * CPU slice and the cache error vector is fetched through that alias,
> > +	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
> > +	 */
> > +	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);
> 
>  This just copies instructions between the same physical memory locations, 
> from an XKPHYS mapping to its corresponding KSEG1 mapping, i.e. the bus 

IP27 is special here:

/*
 * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
 * uncached memory addressing. Hide the definitions on 32-bit compilation
 * of the compat-vdso code.
 */
#ifdef CONFIG_64BIT
#define HSPEC_BASE              _AC(0x9000000000000000, UL)
#define IO_BASE                 _AC(0x9200000000000000, UL)
#define MSPEC_BASE              _AC(0x9400000000000000, UL)
#define UNCAC_BASE              _AC(0x9600000000000000, UL)
#define CAC_BASE                _AC(0xa800000000000000, UL)
#endif

Hub ASIC uses the extra address bits, so the physiacl address is not the same.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]

Re: [PATCH] MIPS: SGI-IP27: Install the cache error vector on every CPU

[Maciej W. Rozycki]

On Sat, 24 Oct 2026, Thomas Bogendoerfer wrote:

> > > diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
> > > index 62733e049570..0fef66b86959 100644
> > > --- a/arch/mips/sgi-ip27/ip27-smp.c
> > > +++ b/arch/mips/sgi-ip27/ip27-smp.c
> > > @@ -133,6 +135,18 @@ static void ip27_init_cpu(void)
> > >  	per_cpu_init();
> > >  }
> > >  
> > > +static void ip27_init_secondary(void)
> > > +{
> > > +	/*
> > > +	 * The hub flips the low 128K of the attribute 0 uncached alias per
> > > +	 * CPU slice and the cache error vector is fetched through that alias,
> > > +	 * so the copy trap_init() made through TO_UNCAC() only serves slice 0.
> > > +	 */
> > > +	memcpy((void *)CKSEG1ADDR(0x100), (void *)TO_UNCAC(0x100), 0x80);
> > 
> >  This just copies instructions between the same physical memory locations, 
> > from an XKPHYS mapping to its corresponding KSEG1 mapping, i.e. the bus 
> 
> IP27 is special here:
> 
> /*
>  * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
>  * uncached memory addressing. Hide the definitions on 32-bit compilation
>  * of the compat-vdso code.
>  */
> #ifdef CONFIG_64BIT
> #define HSPEC_BASE              _AC(0x9000000000000000, UL)
> #define IO_BASE                 _AC(0x9200000000000000, UL)
> #define MSPEC_BASE              _AC(0x9400000000000000, UL)
> #define UNCAC_BASE              _AC(0x9600000000000000, UL)
> #define CAC_BASE                _AC(0xa800000000000000, UL)
> #endif
> 
> Hub ASIC uses the extra address bits, so the physiacl address is not the same.

 Fair enough, though I think that the use of the R10k's uncached attribute 
driven on the bus for what I gather is each CPU's local memory (?) will 
best be documented more clearly through the change (i.e. in the commit 
description and with ip27_init_secondary()).

  Maciej