From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: James Hilliard <james.hilliard1@gmail.com>
Cc: "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Chen-Yu Tsai" <wens@kernel.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH v2 2/3] serial: 8250_dw: configure the Allwinner H616 UART
Date: Sat, 24 Oct 2026 13:54:29 +0300 [thread overview]
Message-ID: <atyOZcmdRMnpF078@ashevche-desk.local> (raw)
In-Reply-To: <20261023-submit-h616-uart-fifo-v1-v2-2-af0593504635@gmail.com>
On Fri, Oct 23, 2026 at 03:19:28PM -0600, James Hilliard wrote:
> H616 has 256-byte transmit and receive FIFOs, but its optional DesignWare
> component parameter register reads as zero. Generic 16550 probing leaves
> the port using the 16-byte FIFO configuration and its trigger-level table.
> DMA attachment also depends on a FIFO size being available during probe,
> so these ports do not reach the existing 8250 DMA path.
>
> Keep PORT_16550A and supply the FIFO size, transmit load and capabilities
> when matching the H616 platform data. Provide receive-trigger callbacks
> for the documented thresholds of 1, 64, 128 and 254 bytes. The normal
> 16550A half-full trigger selects 128 bytes on this integration. Serialize
> trigger changes with termios and hold a runtime PM reference while
> programming FCR, preserving the FIFO contents.
>
> Advertise automatic flow control so CRTSCTS enables MCR.AFCE. The
> DesignWare termios path selects hardware CTS handling, so the capability
> must be present for the corresponding hardware control to be enabled.
>
> Skip optional-register probing for this fixed configuration. H616 has
> debug-divisor and RS485 control registers at the offsets used to detect
> DesignWare hardware RS485 and fractional-divisor support. Probing these
> offsets writes unrelated registers and can select incompatible callbacks.
> Keep the BUSY-safe integer divisor hook and software RS485 handling.
>
> Use the existing SKIP_SET_RATE quirk to keep the UART clock enabled during
> termios changes. Its clock is a gate on the shared APB2 source, rather than
> an independent baud-rate generator.
>
> Attach DMA from the fixed configuration before registering the port.
> Configure single-byte RX and TX bursts because the peripheral request can
> correspond to just one character. The existing startup path requests the
> firmware-described channels and falls back to PIO when they are unavailable
> or the port is a kernel console.
...
> +static int dw8250_h616_set_rxtrig(struct uart_port *p, unsigned char bytes)
> +{
> + struct uart_8250_port *up = up_to_u8250p(p);
> + int i, ret;
Why is 'i' signed?
> + /* Use the nearest lower threshold, as the generic 8250 implementation does. */
> + for (i = 1; i < ARRAY_SIZE(dw8250_h616_rxtrig_bytes); i++)
> + if (bytes < dw8250_h616_rxtrig_bytes[i])
> + break;
> +
> + guard(mutex)(&p->state->port.mutex);
> +
> + ret = pm_runtime_resume_and_get(p->dev);
> + if (ret < 0)
> + return ret;
Don't we have a guard()() for this?
> + scoped_guard(uart_port_lock_irqsave, p) {
> + up->fcr &= ~UART_FCR_TRIGGER_MASK;
> + up->fcr |= (i - 1) << UART_FCR_R_TRIG_SHIFT;
> + /* Changing the trigger alone preserves the FIFO contents. */
> + serial_port_out(p, UART_FCR, up->fcr);
> + }
> + pm_runtime_put(p->dev);
> +
> + return 0;
> +}
...
> static int dw8250_probe(struct platform_device *pdev)
> - if (!data->skip_autocfg)
> - dw8250_setup_port(p);
> -
> - /* If we have a valid fifosize, try hooking up DMA */
> - if (p->fifosize) {
> - data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
> - data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
> - up->dma = &data->data.dma;
> + if (data->pdata == &dw8250_h616_data) {
> + dw8250_h616_setup(up, data);
> + } else {
> + if (!data->skip_autocfg)
> + dw8250_setup_port(p);
> +
> + /* If we have a valid fifosize, try hooking up DMA */
> + if (p->fifosize) {
> + data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
> + data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
> + up->dma = &data->data.dma;
> + }
> }
This looks unscalable and too much churn. What you should do is to add
a .setup() callback member to struct dw8250_platform_data and assign that
to dw8250_setup_port(), and change the
if (!data->skip_autocfg)
dw8250_setup_port(p);
to
if (data->pdata->setup)
data->pdata->setup(...);
which effectively kills that skip_autocfg. This is done in a separate patch.
Then in your patch you won't need this churn.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-24 10:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 21:19 [PATCH v2 0/3] serial: 8250_dw: describe the Allwinner H616 UART configuration James Hilliard
2026-10-23 21:19 ` [PATCH v2 1/3] dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 James Hilliard
2026-10-23 21:19 ` [PATCH v2 2/3] serial: 8250_dw: configure the Allwinner H616 UART James Hilliard
2026-10-24 10:54 ` Andy Shevchenko [this message]
2026-10-23 21:19 ` [PATCH v2 3/3] arm64: dts: allwinner: h616: identify the UART integration James Hilliard
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