From: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
rafael@kernel.org
Cc: acpica-devel@lists.linux.dev, anup.patel@oss.qualcomm.com,
ardb@kernel.org, conor@kernel.org, james.morse@arm.com,
lenb@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com,
robert.moore@intel.com, sunilvl@oss.qualcomm.com,
tony.luck@intel.com, zhangzhanpeng.jasper@bytedance.com
Subject: Re: [PATCH v5 3/9] Introduce a new HEST notification type for RISC-V SSE events.
Date: Tue, 27 Oct 2026 11:02:09 +0530 [thread overview]
Message-ID: <auA3WZf5rLlx4Lve@hu-himchau-blr.qualcomm.com> (raw)
In-Reply-To: <20260924073714.1650588-4-himanshu.chauhan@oss.qualcomm.com>
On Thu, Sep 24, 2026 at 01:07:08PM +0530, Himanshu Chauhan wrote:
> The GHES entry's notification structure contains the notification
> to be used for a given error source. For error sources delivering
> events over SSE, it should contain the new SSE notification type.
> acpi: Introduce SSE in HEST notification types
>
> ACPICA commit f73f39352c1170464afe812cc96b20cc9db1d822
Hi Rafael,
This is merged in ACPICA. Could you please pick it up for Linux kernel?
Once you do that I will drop this patch from here.
Regards
Himanshu
>
> Link: https://github.com/open-acpica/acpica/commit/f73f3935
> Signed-off-by: Himanshu Chauhan <himanshu.chauhan@oss.qualcomm.com>
> ---
> include/acpi/actbl1.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
> index d824838cb7af..105fd51f83ec 100644
> --- a/include/acpi/actbl1.h
> +++ b/include/acpi/actbl1.h
> @@ -1798,7 +1798,8 @@ enum acpi_hest_notify_types {
> ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */
> ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */
> ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED = 11, /* ACPI 6.2 */
> - ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
> + ACPI_HEST_NOTIFY_SSE = 12, /* RISCV SSE */
> + ACPI_HEST_NOTIFY_RESERVED = 13 /* 13 and greater are reserved */
> };
>
> /* Values for config_write_enable bitfield above */
> --
> 2.43.0
>
next prev parent reply other threads:[~2026-10-27 5:32 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 7:37 [PATCH v5 0/9] Add RAS support for RISC-V architecture Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 1/9] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 2/9] riscv: Define arch_apei_get_mem_attribute " Himanshu Chauhan
2026-10-21 9:33 ` Rui Qi
2026-09-24 7:37 ` [PATCH v5 3/9] Introduce a new HEST notification type for RISC-V SSE events Himanshu Chauhan
2026-10-27 5:32 ` Himanshu Chauhan [this message]
2026-09-24 7:37 ` [PATCH v5 4/9] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 5/9] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2026-10-29 23:27 ` Conor Dooley
2026-09-24 7:37 ` [PATCH v5 6/9] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 7/9] riscv: Introduce HEST SSE notification handlers Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 8/9] riscv: Select HAVE_ACPI_APEI required for RAS Himanshu Chauhan
2026-09-24 7:37 ` [PATCH v5 9/9] riscv: Enable APEI GHES driver in defconfig Himanshu Chauhan
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