Re: [PATCH v4 2/9] dt-bindings: iio: adc: ad7768-1: Document multidevice support

[Jonathan Santos <jonath4nns@gmail.com>]

On 10/26, Jonathan Cameron wrote:
> On Tue, 20 Oct 2026 22:56:56 -0300
> Jonathan Santos <Jonathan.Santos@analog.com> wrote:
> 
> > The AD7768-1 family supports aggregating up to four devices on a single
> > SPI controller, with each device occupying a dedicated CS line and a
> > single data lane.
> > 
> > Extend the `reg` property to accept up to 4 entries (one per device).
> > 
> > Add `spi-rx-bus-width` property to declare the per-device lane count.
> > Since each lane is bound to one CS, the number of entries must match
> > `reg`. Make it required when `reg` has more than one entry, along with
> > `spi-cs-composite` property.
> > 
> > Add an example for a four ADAQ7768-1 aggregation, with shared DRDY and
> > SYNC_IN pin.
> > 
> > Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
> > ---
> 
> I'd suggest some asci art might make it more obvious what you mean here.
> 

Ok! in the commit message, right?

> > Changes in v4:
> > * Include spi-cs-composite property to the bindings. The reason for going
> >   this route is stated in the cover letter.
> > * We decided to keep the spi-rx-bus-width property because assuming 1-lane
> >   per CS would break controllers that don't support multiple lanes.
> > 
> > Changes in v3:
> > * New patch.
> > ---
> >  .../bindings/iio/adc/adi,ad7768-1.yaml        | 80 ++++++++++++++++++-
> >  1 file changed, 79 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
> > index 7b72d14e104c..64c1cbeaa576 100644
> > --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
> > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7768-1.yaml
> > @@ -26,7 +26,10 @@ properties:
> >        - adi,adaq7769-1
> >  
> >    reg:
> > -    maxItems: 1
> > +    minItems: 1
> > +    maxItems: 4
> > +    description:
> > +      Chip select number. For multi-device setups, one entry per device.
> >  
> >    clocks:
> >      maxItems: 1
> > @@ -109,6 +112,12 @@ properties:
> >    reset-gpios:
> >      maxItems: 1
> >  
> > +  spi-rx-bus-width:
> > +    description:
> > +      Bus width per CS. For multi-device setups (multiple reg entries), one
> > +      entry per device must be provided. Required when reg has more than
> > +      one entry.
> > +
> >    spi-cpol: true
> >  
> >    spi-cpha: true
> > @@ -203,6 +212,16 @@ allOf:
> >        properties:
> >          pga-gpios: false
> >  
> > +  # Required properties for multi-device setups
> > +  - if:
> > +      properties:
> > +        reg:
> > +          minItems: 2
> > +    then:
> > +      required:
> > +        - spi-rx-bus-width
> > +        - spi-cs-composite
> > +
> >  unevaluatedProperties: false
> >  
> >  examples:
> > @@ -244,4 +263,63 @@ examples:
> >              };
> >          };
> >      };
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/gpio/gpio.h>
> > +    #include <dt-bindings/iio/adc/adi,ad7768-1.h>
> > +    /*
> > +     * Four ADAQ7768-1 devices aggregated on a single SPI controller.
> > +     * Each device occupies one CS and one data lane; DRDY and SYNC_IN
> > +     * pins are wired together across all four devices.
> 
> For DRDY, wired together how?   I assume that only gets set when
> they are all ready?
> 

They are combined through an AND gate, so yes, it only gets set when
they are all ready. We make sure by using the SYNC_IN to synchronize
them.

> > +     */
> > +    spi {
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +
> > +        adc@0 {
> > +            compatible = "adi,adaq7768-1";
> > +            reg = <0>, <1>, <2>, <3>;
> > +            spi-rx-bus-width = <1>, <1>, <1>, <1>;
> > +            spi-cs-composite;
> > +            spi-max-frequency = <2000000>;
> > +            spi-cpol;
> > +            spi-cpha;
> > +            vref-supply = <&adc_vref>;
> > +            pga-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>,
> > +                        <&gpio 11 GPIO_ACTIVE_HIGH>,
> > +                        <&gpio 12 GPIO_ACTIVE_HIGH>;
> > +            interrupts = <25 IRQ_TYPE_EDGE_RISING>;
> > +            interrupt-parent = <&gpio>;
> > +            #trigger-source-cells = <1>;
> > +            adi,sync-in-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
> > +            reset-gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
> > +            clocks = <&ad7768_mclk>;
> > +            clock-names = "mclk";
> > +            gpio-controller;
> > +            #gpio-cells = <2>;
> > +            #io-channel-cells = <1>;
> > +            #address-cells = <1>;
> > +            #size-cells = <0>;
> > +
> > +            channel@0 {
> > +                reg = <0>;
> > +                label = "channel_0";
> > +            };
> > +
> > +            channel@1 {
> > +                reg = <1>;
> > +                label = "channel_1";
> > +            };
> > +
> > +            channel@2 {
> > +                reg = <2>;
> > +                label = "channel_2";
> > +            };
> > +
> > +            channel@3 {
> > +                reg = <3>;
> > +                label = "channel_3";
> > +            };
> > +        };
> > +    };
> >  ...