[PATCH v4 1/9] spi: dt-bindings: Add spi-cs-composite property

[Jonathan Santos <Jonathan.Santos@analog.com>]

Some setups combine several SPI devices into one logical device, with
each chip on its own CS line. All of those CS lines must be asserted at
the same time, so that one transfer reaches every chip.

Add the 'spi-cs-composite' boolean property. When it is set, every chip
select listed in 'reg' is asserted together on each transfer.

Signed-off-by: Jonathan Santos <Jonathan.Santos@analog.com>
---
Changes in v4:
* New patch. This has been included because without an explicit property,
  every device with more than one 'reg' entry would have all its chip
  selects asserted together. That breaks devices that use ancillary
  devices for the extra CS lines, so the composite behavior is now opt-in.
---
 .../devicetree/bindings/spi/spi-peripheral-props.yaml     | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
index 4894196c8f9c..456cb9095632 100644
--- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml
@@ -60,6 +60,14 @@ properties:
       Delay in nanoseconds to be introduced by the controller after CS is
       de-asserted.
 
+  spi-cs-composite:
+    description: Some SPI devices can be aggregated into a single logical
+      device by asserting all their chip selects simultaneously. When this
+      property is present, all chip selects listed in the 'reg' property are
+      asserted together on every transfer, treating the group as one composite
+      device.
+    type: boolean
+
   spi-rx-bus-width:
     description:
       Bus width to the SPI bus used for read transfers.
-- 
2.34.1