Re: [PATCH] cxl/port: Unmask AER internal errors for VH endpoints

[Richard Cheng <icheng@nvidia.com>]

On Sat, Oct 31, 2026 at 03:11:29AM +0800, Li Ming wrote:
> On 10/30/2026 5:59 PM, Richard Cheng wrote:
> > CXL protocol errors are reported through PCIe AER internal errors.
> > Unmasking the endpoint's CXL RAS register alone leaves the AER internal
> > errors masked, thus the notification can't reach the Root Port.
> >
> > Unmask AER internal errors during native endpoint RAS setup for VH
> > devices. Allow cxl_port to use pci_aer_unmask_internal_errors() through
> > its module-restricted export.
> >
> > Verified with QEMU mem-data-ecc injection: the Root Port AER interrupt
> > fires, the CXL correctable-error trace is emitted, and the endpoint's
> > CorrIntErr counter increments.
> 
> I found the similiar implementation[1] in CXL RAS support for VH patchset[2], seems like it is under review.
>

Ohh ok, then I think we can drop this one.

Thanks.
 
> 
> [1]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-9-terry.bowman@amd.com/
> 
> [2]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-1-terry.bowman@amd.com/
> 
> 
> Ming
> 
> >
> > Signed-off-by: Richard Cheng <icheng@nvidia.com>
> > ---
> >  drivers/cxl/port.c     | 7 +++++++
> >  drivers/pci/pcie/aer.c | 3 ++-
> >  2 files changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c
> > index c48216e5078f..c94a310061b0 100644
> > --- a/drivers/cxl/port.c
> > +++ b/drivers/cxl/port.c
> > @@ -121,6 +121,13 @@ static int cxl_ras_unmask(struct cxl_port *port)
> >  			orig_val, val);
> >  	}
> >  
> > +	/*
> > +	 * RCH errors are reported by the RCEC. VH endpoints report CXL
> > +	 * protocol errors as PCIe AER internal errors.
> > +	 */
> > +	if (!is_cxl_restricted(pdev))
> > +		pci_aer_unmask_internal_errors(pdev);
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> > index db4f607f889c..94eca22422b7 100644
> > --- a/drivers/pci/pcie/aer.c
> > +++ b/drivers/pci/pcie/aer.c
> > @@ -1287,7 +1287,8 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)
> >   * Internal errors are too device-specific to enable generally, however for CXL
> >   * their behavior is standardized for conveying CXL protocol errors.
> >   */
> > -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core");
> > +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors,
> > +			  "cxl_core,cxl_port");
> >  
> >  #ifdef CONFIG_CXL_RAS
> >  bool is_aer_internal_error(struct aer_err_info *info)
> >
> > base-commit: f0c48323b0402349530abc60ea908b5f5f40c395
> 
>