Re: [PATCH 1/3] dmaengine: dw-axi-dmac: poll the correct enable bit during termination

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Sun, Nov 08, 2026 at 10:02:36PM -0700, James Hilliard wrote:
> For channels 16 through 31, the channel enable bits occupy bits 32 through
> 47 of the extended DMAC_CHEN register. dma_chan_terminate_all() only reads
> the low word and tests BIT(chan->id), so it can conclude that an upper-bank
> channel has stopped while its actual enable bit remains set. Descriptors
> can then be freed while hardware still owns them.
> 
> Poll axi_chan_is_hw_enable(), which already handles both register banks
> and the smaller channel layouts, instead of constructing another mask.

...

> -	ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
> -					!(val & chan_active), 1000, 50000);
> +	ret = read_poll_timeout_atomic(axi_chan_is_hw_enable, enabled, !enabled,
> +				      1000, 50000, false, chan);

With a single argument it's readx_poll_timeout_atomic().
While at it, you may use 1 * USEC_PER_MSEC and 50 * USEC_PER_MSEC instead of
plain numbers.

	ret = readx_poll_timeout_atomic(axi_chan_is_hw_enable, chan,
					enabled, !enabled,
					1 * USEC_PER_MSEC, 50 * USEC_PER_MSEC);

-- 
With Best Regards,
Andy Shevchenko