From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: James Hilliard <james.hilliard1@gmail.com>
Cc: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@kernel.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH v8 06/11] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth
Date: Tue, 10 Nov 2026 01:10:18 +0200 [thread overview]
Message-ID: <avJS2vUE-UrPVXqi@ashevche-desk.local> (raw)
In-Reply-To: <20261105-submit-h616-uart-fifo-v1-v8-6-14024d2b184b@gmail.com>
On Thu, Nov 05, 2026 at 01:52:07PM -0700, James Hilliard wrote:
> DW_apb_uart uses receive thresholds of one byte, one quarter full,
> one half full and two bytes below full. The generic 16550A table describes
> these encodings only for a 16-byte FIFO. For example, the half-full setting
> on a 64-byte DW FIFO is reported as eight bytes instead of 32, and a sysfs
> request for 32 bytes selects the 62-byte encoding.
>
> Build a per-port threshold table from the discovered FIFO depth in dwlib
> and install receive-trigger callbacks for CPR-described FIFOs, including
> LPSS ports. Keep the setup helper available to integrations which obtain
> the depth without probing the optional DW registers. Validate that each
> threshold is positive and representable before constructing the table.
>
> Serialize FCR updates with termios and the port lock, acquire a runtime PM
> reference before accessing the device, and propagate resume errors without
> changing the shadow or hardware. Update only the trigger field so changing
> the threshold preserves the FIFO contents.
>
> The FCR mapping is documented in the DW_apb_uart databook, section 6,
> FIFO Control Register. The existing default FCR encoding is unchanged.
...
> +static int dw8250_set_rxtrig(struct uart_port *p, u16 bytes)
> +{
> + struct dw8250_port_data *pd = p->private_data;
> + struct uart_8250_port *up = up_to_u8250p(p);
> + int fcr, ret;
> +
> + fcr = serial8250_bytes_to_fcr(pd->rxtrig_bytes, bytes);
> + if (fcr < 0)
> + return fcr;
> +
> + guard(mutex)(&p->state->port.mutex);
> +
> + PM_RUNTIME_ACQUIRE_IF_ENABLED(p->dev, pm);
> + ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
> + if (ret)
> + return ret;
> +
> + guard(uart_port_lock_irqsave)(p);
> +
> + up->fcr &= ~UART_FCR_TRIGGER_MASK;
> + up->fcr |= fcr;
FIELD_MODIFY()
> + /* Changing the trigger alone preserves the FIFO contents */
> + serial_port_out(p, UART_FCR, up->fcr);
> +
> + return 0;
> +}
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-11-09 23:10 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 20:52 [PATCH v8 00/11] serial: 8250_dw: share RX trigger setup and describe Allwinner UARTs James Hilliard
2026-11-05 20:52 ` [PATCH v8 01/11] serial: 8250_dw: allow port setup to report errors James Hilliard
2026-11-09 23:05 ` Andy Shevchenko
2026-11-09 23:06 ` Andy Shevchenko
2026-11-05 20:52 ` [PATCH v8 02/11] serial: 8250_dw: select port setup through platform data James Hilliard
2026-11-05 20:52 ` [PATCH v8 03/11] serial: 8250: widen RX trigger byte counts to 16 bits James Hilliard
2026-11-05 20:52 ` [PATCH v8 04/11] serial: 8250: share the RX trigger conversion helper James Hilliard
2026-11-05 20:52 ` [PATCH v8 05/11] serial: 8250: expose RX trigger controls for custom callbacks James Hilliard
2026-11-05 20:52 ` [PATCH v8 06/11] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth James Hilliard
2026-11-09 23:10 ` Andy Shevchenko [this message]
2026-11-05 20:52 ` [PATCH v8 07/11] dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 James Hilliard
2026-11-05 20:52 ` [PATCH v8 08/11] serial: 8250_dw: configure the Allwinner H616 UART James Hilliard
2026-11-05 20:52 ` [PATCH v8 09/11] dt-bindings: serial: snps-dw-apb-uart: add Allwinner A523 James Hilliard
2026-11-05 20:52 ` [PATCH v8 10/11] serial: 8250_dw: discover Allwinner A523 FIFO depths through FCC James Hilliard
2026-11-05 20:52 ` [PATCH v8 11/11] serial: 8250_dw: configure RX trigger thresholds for Octeon James Hilliard
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