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From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: aiyengar1990@gmail.com
Cc: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	 "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Heiko Stuebner <heiko@sntech.de>,
	Niklas Cassel <cassel@kernel.org>,
	 linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 5/5] arm64: dts: rockchip: add the clock of the RK3588 PCIe SMMU
Date: Tue, 10 Nov 2026 16:07:00 +0100	[thread overview]
Message-ID: <avMyK-ZQh8qVrFmw@venus> (raw)
In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-5-628819ca44b9@gmail.com>

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Hi,

On Tue, Nov 10, 2026 at 07:11:52AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> The PCIe MMU-600 runs from ACLK_MMU_PCIE, which is also the parent of
> the PCIe controllers' master clocks. When no PCIe controller is enabled,
> nothing holds it and it gets gated as unused after boot, while
> arm-smmu-v3 is still bound to the SMMU.
> 
> Describe the clock, so that the SMMU driver keeps it running.
> 
> Fixes: da92d3dfc871 ("arm64: dts: rockchip: enable the mmu600_pcie IOMMU on the rk3588 SoC")
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Greetings,

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index bcd342c025c9..8eed22ca69ab 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -559,6 +559,7 @@ mmu600_pcie: iommu@fc900000 {
>  			     <GIC_SPI 374 IRQ_TYPE_EDGE_RISING 0>,
>  			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
>  		interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> +		clocks = <&cru ACLK_MMU_PCIE>;
>  		#iommu-cells = <1>;
>  		power-domains = <&power RK3588_PD_PCIE>;
>  	};
> 
> -- 
> 2.55.0
> 
> 
> 

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  reply	other threads:[~2026-11-10 15:07 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10  7:11 [PATCH 0/5] iommu/arm-smmu-v3: power domain and " Arun Iyengar via B4 Relay
2026-11-10  7:11 ` [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain Arun Iyengar via B4 Relay
2026-11-10 14:51   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks Arun Iyengar via B4 Relay
2026-11-10 14:55   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks Arun Iyengar via B4 Relay
2026-11-10 14:53   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU Arun Iyengar via B4 Relay
2026-11-10 15:00   ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 5/5] arm64: dts: rockchip: add the clock of " Arun Iyengar via B4 Relay
2026-11-10 15:07   ` Sebastian Reichel [this message]
2026-11-10  8:40 ` [PATCH 0/5] iommu/arm-smmu-v3: power domain and " Shawn Lin
2026-11-10  8:49   ` Heiko Stübner
2026-11-10 15:13 ` Sebastian Reichel

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