* [PATCH v6 1/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 2/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family Ricardo Pardini via B4 Relay
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
behind pcie2x1l0 and pcie2x1l2.
Describe the PCI function nodes and attach ethernet0/ethernet1
aliases, so that U-Boot's fdt_fixup_ethernet() can fill in their MAC
addresses from its ethaddr/eth1addr environment.
The labels follow the schematic and case markings: ETH1 (pcie2x1l2) is
rtl_eth1/ethernet0 and ETH2 (pcie2x1l0) is rtl_eth2/ethernet1.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
index 13be56af095b..18e427e94dcf 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
@@ -20,6 +20,8 @@ / {
compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
aliases {
+ ethernet0 = &rtl_eth1;
+ ethernet1 = &rtl_eth2;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
@@ -617,6 +619,20 @@ &pcie2x1l0 {
reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_s3>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x21 0x2f>;
+
+ rtl_eth2: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x210000 0 0 0 0>;
+ };
+ };
};
&pcie2x1l1 {
@@ -633,6 +649,20 @@ &pcie2x1l2 {
reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_s3>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x41 0x4f>;
+
+ rtl_eth1: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x410000 0 0 0 0>;
+ };
+ };
};
&pcie30phy {
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v6 2/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 1/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6 Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
2026-11-11 22:44 ` Sebastian Reichel
2026-11-09 12:32 ` [PATCH v6 3/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588 Ricardo Pardini via B4 Relay
` (3 subsequent siblings)
5 siblings, 1 reply; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The Radxa ROCK 5B, 5B+ and 5T carry an on-board Realtek RTL8125 NIC
behind pcie2x1l2; the ROCK 5T has a second one behind pcie2x1l1.
Describe the PCI function nodes and attach ethernet0 (and, on the
ROCK 5T, ethernet1) aliases, so that U-Boot's fdt_fixup_ethernet() can
fill in their MAC addresses from its ethaddr/eth1addr environment.
The shared NIC goes in rk3588-rock-5b-5bp-5t.dtsi, the ROCK 5T's second
NIC in rk3588-rock-5t.dts.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
.../arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts | 18 ++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index b8d90936fc20..e8a3eb33e402 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -10,6 +10,7 @@
/ {
aliases {
+ ethernet0 = &rtl_eth0;
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
@@ -488,6 +489,20 @@ &pcie2x1l2 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x41 0x4f>;
+
+ rtl_eth0: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x410000 0 0 0 0>;
+ };
+ };
};
&pcie30phy {
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
index 425036146b6d..b1a3e4b2165f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -8,6 +8,10 @@ / {
model = "Radxa ROCK 5T";
compatible = "radxa,rock-5t", "rockchip,rk3588";
+ aliases {
+ ethernet1 = &rtl_eth1;
+ };
+
analog-sound {
compatible = "audio-graph-card";
label = "rk3588-es8316";
@@ -76,6 +80,20 @@ &pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x300000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x31 0x3f>;
+
+ rtl_eth1: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x310000 0 0 0 0>;
+ };
+ };
};
&pcie30phy {
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v6 2/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family
2026-11-09 12:32 ` [PATCH v6 2/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family Ricardo Pardini via B4 Relay
@ 2026-11-11 22:44 ` Sebastian Reichel
0 siblings, 0 replies; 8+ messages in thread
From: Sebastian Reichel @ 2026-11-11 22:44 UTC (permalink / raw)
To: ricardo
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3218 bytes --]
Hi,
On Mon, Nov 09, 2026 at 01:32:17PM +0100, Ricardo Pardini via B4 Relay wrote:
> From: Ricardo Pardini <ricardo@pardini.net>
>
> The Radxa ROCK 5B, 5B+ and 5T carry an on-board Realtek RTL8125 NIC
> behind pcie2x1l2; the ROCK 5T has a second one behind pcie2x1l1.
>
> Describe the PCI function nodes and attach ethernet0 (and, on the
> ROCK 5T, ethernet1) aliases, so that U-Boot's fdt_fixup_ethernet() can
> fill in their MAC addresses from its ethaddr/eth1addr environment.
>
> The shared NIC goes in rk3588-rock-5b-5bp-5t.dtsi, the ROCK 5T's second
> NIC in rk3588-rock-5t.dts.
>
> Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
> ---
root@rock5b+ ~# lspci -nv -d 10ec:8125
0004:41:00.0 0200: 10ec:8125 (rev 05)
Subsystem: 10ec:0123
Device tree node: /sys/firmware/devicetree/base/pcie@fe190000/pcie@0,0/ethernet@0,0
...
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> # Rock 5B+
Greetings,
-- Sebastian
> .../arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 15 +++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts | 18 ++++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
> index b8d90936fc20..e8a3eb33e402 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
> @@ -10,6 +10,7 @@
>
> / {
> aliases {
> + ethernet0 = &rtl_eth0;
> mmc0 = &sdhci;
> mmc1 = &sdmmc;
> mmc2 = &sdio;
> @@ -488,6 +489,20 @@ &pcie2x1l2 {
> reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
> vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
> status = "okay";
> +
> + pcie@0,0 {
> + reg = <0x400000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + device_type = "pci";
> + bus-range = <0x41 0x4f>;
> +
> + rtl_eth0: ethernet@0,0 {
> + compatible = "pci10ec,8125";
> + reg = <0x410000 0 0 0 0>;
> + };
> + };
> };
>
> &pcie30phy {
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> index 425036146b6d..b1a3e4b2165f 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
> @@ -8,6 +8,10 @@ / {
> model = "Radxa ROCK 5T";
> compatible = "radxa,rock-5t", "rockchip,rk3588";
>
> + aliases {
> + ethernet1 = &rtl_eth1;
> + };
> +
> analog-sound {
> compatible = "audio-graph-card";
> label = "rk3588-es8316";
> @@ -76,6 +80,20 @@ &pcie2x1l1 {
> reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
> vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
> status = "okay";
> +
> + pcie@0,0 {
> + reg = <0x300000 0 0 0 0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + device_type = "pci";
> + bus-range = <0x31 0x3f>;
> +
> + rtl_eth1: ethernet@0,0 {
> + compatible = "pci10ec,8125";
> + reg = <0x310000 0 0 0 0>;
> + };
> + };
> };
>
> &pcie30phy {
>
> --
> 2.47.3
>
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 3/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 1/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6 Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 2/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 4/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S Ricardo Pardini via B4 Relay
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The FriendlyElec CM3588 SoM carries one on-board Realtek RTL8125 NIC
behind pcie2x1l2.
Describe the PCI function node and attach an ethernet0 alias, so that
U-Boot's fdt_fixup_ethernet() can fill in its MAC address from its
ethaddr environment.
The node goes in the SoM dtsi, as the RTL8125 sits on the SoM, not on
the CM3588-NAS carrier.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
.../boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
index 49cf4b85c4e9..d6cff0f5dc86 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588.dtsi
@@ -18,6 +18,7 @@ / {
compatible = "friendlyarm,cm3588", "rockchip,rk3588";
aliases {
+ ethernet0 = &rtl_eth0;
mmc0 = &sdhci;
mmc1 = &sdmmc;
};
@@ -257,6 +258,20 @@ &pcie2x1l2 {
reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_pcie20>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x41 0x4f>;
+
+ rtl_eth0: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x410000 0 0 0 0>;
+ };
+ };
};
&pd_gpu {
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v6 4/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
` (2 preceding siblings ...)
2026-11-09 12:32 ` [PATCH v6 3/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588 Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 5/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 6/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX Ricardo Pardini via B4 Relay
5 siblings, 0 replies; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The FriendlyElec NanoPi R5S carries two on-board Realtek RTL8125
NICs behind pcie2x1 and pcie3x1.
Describe the PCI function nodes and attach ethernet1/ethernet2
aliases, so that U-Boot's fdt_fixup_ethernet() can fill in their MAC
addresses from its eth1addr/eth2addr environment.
ethernet0 stays mapped to the on-SoC gmac0.
Note that mainline U-Boot's rockchip_setup_macaddr() derives only
ethaddr and eth1addr from the CPU ID, so ethernet2 only gets a stable
MAC if eth2addr is set in the U-Boot environment.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index 90ce6f0e1dcf..e588ee7fadc5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -15,6 +15,8 @@ / {
aliases {
ethernet0 = &gmac0;
+ ethernet1 = &rtl_eth1;
+ ethernet2 = &rtl_eth2;
};
gpio-keys {
@@ -107,6 +109,20 @@ &pcie2x1 {
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x01 0x0f>;
+
+ rtl_eth1: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x010000 0 0 0 0>;
+ };
+ };
};
&pcie30phy {
@@ -119,6 +135,20 @@ &pcie3x1 {
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x11 0x1f>;
+
+ rtl_eth2: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x110000 0 0 0 0>;
+ };
+ };
};
&pcie3x2 {
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v6 5/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
` (3 preceding siblings ...)
2026-11-09 12:32 ` [PATCH v6 4/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
2026-11-09 12:32 ` [PATCH v6 6/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX Ricardo Pardini via B4 Relay
5 siblings, 0 replies; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The FriendlyElec NanoPi R6C carries one on-board Realtek RTL8125 NIC
(the LAN port) behind pcie2x1l1.
Describe the PCI function node and attach an ethernet1 alias, so that
U-Boot's fdt_fixup_ethernet() can fill in its MAC address from its
eth1addr environment.
ethernet0 stays mapped to the on-SoC gmac1 (the WAN port). The node
goes in this .dts rather than the shared rk3588s-nanopi-r6.dtsi, since
on the R6C the dtsi's second RTL8125-capable lane is empty compared to
the R6S.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
index ccc5e4627517..48d87f7923db 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
@@ -7,8 +7,28 @@
/ {
model = "FriendlyElec NanoPi R6C";
compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
+
+ aliases {
+ ethernet1 = &rtl_eth1;
+ };
};
&lan2_led {
label = "user_led";
};
+
+&pcie2x1l1 {
+ pcie@0,0 {
+ reg = <0x300000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x31 0x3f>;
+
+ rtl_eth1: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x310000 0 0 0 0>;
+ };
+ };
+};
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v6 6/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX
2026-11-09 12:32 [PATCH v6 0/6] describe RTL8125 PCIe NICs on Rockchip boards Ricardo Pardini via B4 Relay
` (4 preceding siblings ...)
2026-11-09 12:32 ` [PATCH v6 5/6] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C Ricardo Pardini via B4 Relay
@ 2026-11-09 12:32 ` Ricardo Pardini via B4 Relay
5 siblings, 0 replies; 8+ messages in thread
From: Ricardo Pardini via B4 Relay @ 2026-11-09 12:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: Sebastian Reichel, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Ricardo Pardini
From: Ricardo Pardini <ricardo@pardini.net>
The Radxa ROCK 5 ITX carries two on-board Realtek RTL8125 NICs behind
pcie2x1l1 and pcie2x1l2.
Describe the PCI function nodes and attach ethernet0/ethernet1
aliases, so that U-Boot's fdt_fixup_ethernet() can fill in their MAC
addresses from its ethaddr/eth1addr environment.
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
index 9d3d26d4600b..dd9767edd42c 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -20,6 +20,8 @@ / {
compatible = "radxa,rock-5-itx", "rockchip,rk3588";
aliases {
+ ethernet0 = &rtl_eth0;
+ ethernet1 = &rtl_eth1;
mmc0 = &sdhci;
mmc1 = &sdmmc;
mmc2 = &sdio;
@@ -631,6 +633,20 @@ &pcie2x1l1 {
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_lan>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x300000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x31 0x3f>;
+
+ rtl_eth0: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x310000 0 0 0 0>;
+ };
+ };
};
/* RTL8125B_2 */
@@ -640,6 +656,20 @@ &pcie2x1l2 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_lan_phy2>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+ bus-range = <0x41 0x4f>;
+
+ rtl_eth1: ethernet@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x410000 0 0 0 0>;
+ };
+ };
};
&pcie30phy {
--
2.47.3
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