* [PATCH 0/2] Fix Panfrost boot hang on NanoPi M5
@ 2026-10-19 9:24 Leonard Lausen
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
2026-10-19 9:24 ` [PATCH 2/2] arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5 Leonard Lausen
0 siblings, 2 replies; 8+ messages in thread
From: Leonard Lausen @ 2026-10-19 9:24 UTC (permalink / raw)
To: ulfh, heiko
Cc: leonard, robh, krzk+dt, conor+dt, detlev.casanova, finley.xiao,
zhangqing, inindev, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-pm, gahing
On the NanoPi M5, boot hangs during Panfrost initialization. Before this
fix, booting required blacklisting Panfrost on the kernel command line.
Loading Panfrost after boot reports a GPU power-domain acknowledgment
timeout.
Enable regulator management for the RK3576 GPU power domain and connect
its supply to the NanoPi M5 GPU rail.
The regulator-capable descriptor is based on Jiaxing Hu's RK3576 NPU work:
https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
On the NanoPi M5 with CONFIG_DRM_PANFROST=m, boot and Panfrost
initialization succeed, and GPU workloads run successfully. W=1 driver
and DTB builds and schema validation pass.
Leonard Lausen (2):
pmdomain: rockchip: Manage the RK3576 GPU domain supply
arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5
arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
3 files changed, 12 insertions(+), 4 deletions(-)
base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-10-19 9:24 [PATCH 0/2] Fix Panfrost boot hang on NanoPi M5 Leonard Lausen
@ 2026-10-19 9:24 ` Leonard Lausen
2026-10-19 10:05 ` Shawn Lin
` (2 more replies)
2026-10-19 9:24 ` [PATCH 2/2] arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5 Leonard Lausen
1 sibling, 3 replies; 8+ messages in thread
From: Leonard Lausen @ 2026-10-19 9:24 UTC (permalink / raw)
To: ulfh, heiko
Cc: leonard, robh, krzk+dt, conor+dt, detlev.casanova, finley.xiao,
zhangqing, inindev, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-pm, gahing
On the NanoPi M5, boot hangs during Panfrost initialization. Before this
fix, booting required blacklisting Panfrost on the kernel command line.
Loading Panfrost after boot reports a GPU power-domain acknowledgment
timeout:
failed to get ack on domain 'gpu', val=0x113ff
Add regulator support to the RK3576 domain descriptors and mark the GPU
domain as regulator-dependent. This lets the existing Rockchip
power-domain regulator handling manage the GPU domain supply.
A corresponding domain-supply property is needed in the board DT.
The regulator-capable descriptors are based on the regulator support in
Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
delay changes.
Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
Signed-off-by: Leonard Lausen <leonard@lausen.nl>
---
drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
index e193f978d5f35..b41f9fcb62bfe 100644
--- a/drivers/pmdomain/rockchip/pm-domains.c
+++ b/drivers/pmdomain/rockchip/pm-domains.c
@@ -176,41 +176,42 @@ struct rockchip_pmu {
.mem_offset = m_offset, \
.mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
.req_mask = (req), \
.idle_mask = (idle), \
.ack_mask = (ack), \
.active_wakeup = wakeup, \
.need_regulator = regulator, \
}
-#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
+#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \
{ \
.name = _name, \
.pwr_offset = p_offset, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
.mem_offset = m_offset, \
.mem_status_mask = (m_status), \
.repair_status_mask = (r_status), \
.req_offset = r_offset, \
.req_w_mask = (req) << 16, \
.req_mask = (req), \
.idle_mask = (idle), \
.clk_ungate_mask = (g_mask), \
.ack_mask = (ack), \
.active_wakeup = wakeup, \
+ .need_regulator = regulator, \
}
#define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
{ \
.name = _name, \
.pwr_w_mask = (pwr) << 16, \
.pwr_mask = (pwr), \
.status_mask = (status), \
.req_w_mask = (req) << 16, \
.req_mask = (req), \
.idle_mask = (idle), \
.ack_mask = (ack), \
@@ -250,25 +251,28 @@ struct rockchip_pmu {
DOMAIN(name, pwr, status, req, req, req, wakeup)
#define DOMAIN_RK3528(name, pwr, req) \
DOMAIN_M(name, pwr, pwr, req, req, req, false)
#define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
#define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
- DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
+ DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, false)
+
+#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
+ DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, true)
/*
* Dynamic Memory Controller may need to coordinate with us -- see
* rockchip_pmu_block().
*
* dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
* block() while we're initializing the PMU.
*/
static DEFINE_MUTEX(dmc_pmu_mutex);
static struct rockchip_pmu *dmc_pmu;
/*
@@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
[RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
[RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
[RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
[RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
[RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
[RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
[RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
[RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
[RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
[RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
[RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
[RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
- [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
+ [RK3576_PD_GPU] = DOMAIN_RK3576_R("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
};
static const struct rockchip_domain_info rk3588_pm_domains[] = {
[RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
[RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
[RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
[RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
[RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
[RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
[RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
[RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
[RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5
2026-10-19 9:24 [PATCH 0/2] Fix Panfrost boot hang on NanoPi M5 Leonard Lausen
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
@ 2026-10-19 9:24 ` Leonard Lausen
1 sibling, 0 replies; 8+ messages in thread
From: Leonard Lausen @ 2026-10-19 9:24 UTC (permalink / raw)
To: ulfh, heiko
Cc: leonard, robh, krzk+dt, conor+dt, detlev.casanova, finley.xiao,
zhangqing, inindev, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-pm, gahing
On the NanoPi M5, boot hangs during Panfrost initialization. Before this
fix, booting required blacklisting Panfrost on the kernel command line.
Loading Panfrost after boot reports a GPU power-domain acknowledgment
timeout:
failed to get ack on domain 'gpu', val=0x113ff
Label the GPU power domain and connect its domain-supply to vdd_gpu_s0,
so the power-domain driver can manage the GPU rail. Keep mali-supply for
Panfrost's regulator use.
Fixes: 96cbdfdd3ac2 ("arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support")
Signed-off-by: Leonard Lausen <leonard@lausen.nl>
---
arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts | 4 ++++
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
index 227fe6f3ec7c7..c056b3eeafed3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-m5.dts
@@ -791,24 +791,28 @@ rgmii_phy1: phy@1 {
reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>;
};
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_perstn>;
reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_m2_keym>;
status = "okay";
};
+&pd_gpu {
+ domain-supply = <&vdd_gpu_s0>;
+};
+
&pinctrl {
gmac {
gmac0_int: gmac0-int {
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
gmac0_rst: gmac0-rst {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};
gmac1_int: gmac1-int {
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
};
gmac1_rst: gmac1-rst {
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index b0c0d3c8b1b14..0dd7e9ca908ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1075,25 +1075,25 @@ power-domain@RK3576_PD_NPU0 {
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_NPU1 {
reg = <RK3576_PD_NPU1>;
clocks = <&cru HCLK_RKNN_ROOT>,
<&cru ACLK_RKNN1>;
pm_qos = <&qos_npu_m1>;
#power-domain-cells = <0>;
};
};
};
- power-domain@RK3576_PD_GPU {
+ pd_gpu: power-domain@RK3576_PD_GPU {
reg = <RK3576_PD_GPU>;
clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
pm_qos = <&qos_gpu>;
#power-domain-cells = <0>;
};
power-domain@RK3576_PD_NVM {
reg = <RK3576_PD_NVM>;
clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
pm_qos = <&qos_emmc>,
<&qos_fspi0>;
#power-domain-cells = <1>;
--
2.47.3
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
@ 2026-10-19 10:05 ` Shawn Lin
2026-11-12 15:19 ` Ulf Hansson
2026-11-12 18:12 ` Sebastian Reichel
2 siblings, 0 replies; 8+ messages in thread
From: Shawn Lin @ 2026-10-19 10:05 UTC (permalink / raw)
To: Leonard Lausen, heiko, ulfh
Cc: shawn.lin, robh, krzk+dt, conor+dt, detlev.casanova, finley.xiao,
zhangqing, inindev, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-pm, gahing
在 2026/10/19 星期一 17:24, Leonard Lausen 写道:
> On the NanoPi M5, boot hangs during Panfrost initialization. Before this
> fix, booting required blacklisting Panfrost on the kernel command line.
> Loading Panfrost after boot reports a GPU power-domain acknowledgment
> timeout:
>
> failed to get ack on domain 'gpu', val=0x113ff
>
> Add regulator support to the RK3576 domain descriptors and mark the GPU
> domain as regulator-dependent. This lets the existing Rockchip
> power-domain regulator handling manage the GPU domain supply.
>
> A corresponding domain-supply property is needed in the board DT.
>
> The regulator-capable descriptors are based on the regulator support in
> Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
> delay changes.
>
It looks correct to me after checking TRM that PD_GPU need a VD_GPU on
this Soc.
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
> Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
> Signed-off-by: Leonard Lausen <leonard@lausen.nl>
>
> ---
> drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index e193f978d5f35..b41f9fcb62bfe 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
> @@ -176,41 +176,42 @@ struct rockchip_pmu {
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> .need_regulator = regulator, \
> }
>
> -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
> +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_offset = p_offset, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .clk_ungate_mask = (g_mask), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> + .need_regulator = regulator, \
> }
>
> #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> @@ -250,25 +251,28 @@ struct rockchip_pmu {
> DOMAIN(name, pwr, status, req, req, req, wakeup)
>
> #define DOMAIN_RK3528(name, pwr, req) \
> DOMAIN_M(name, pwr, pwr, req, req, req, false)
>
> #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
> DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
>
> #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
> DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
>
> #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, false)
> +
> +#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, true)
>
> /*
> * Dynamic Memory Controller may need to coordinate with us -- see
> * rockchip_pmu_block().
> *
> * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
> * block() while we're initializing the PMU.
> */
> static DEFINE_MUTEX(dmc_pmu_mutex);
> static struct rockchip_pmu *dmc_pmu;
>
> /*
> @@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
> [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
> [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
> [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
> [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
> [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
> [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
> [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
> [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
> [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
> [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
> [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
> - [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> + [RK3576_PD_GPU] = DOMAIN_RK3576_R("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> };
>
> static const struct rockchip_domain_info rk3588_pm_domains[] = {
> [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
> [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
> [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
2026-10-19 10:05 ` Shawn Lin
@ 2026-11-12 15:19 ` Ulf Hansson
2026-11-12 16:10 ` Leonard Lausen
2026-11-12 18:15 ` Sebastian Reichel
2026-11-12 18:12 ` Sebastian Reichel
2 siblings, 2 replies; 8+ messages in thread
From: Ulf Hansson @ 2026-11-12 15:19 UTC (permalink / raw)
To: Leonard Lausen
Cc: ulfh, heiko, robh, krzk+dt, conor+dt, detlev.casanova,
finley.xiao, zhangqing, inindev, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-pm, gahing
On Mon, Oct 19, 2026 at 11:24 AM Leonard Lausen <leonard@lausen.nl> wrote:
>
> On the NanoPi M5, boot hangs during Panfrost initialization. Before this
> fix, booting required blacklisting Panfrost on the kernel command line.
> Loading Panfrost after boot reports a GPU power-domain acknowledgment
> timeout:
>
> failed to get ack on domain 'gpu', val=0x113ff
>
> Add regulator support to the RK3576 domain descriptors and mark the GPU
> domain as regulator-dependent. This lets the existing Rockchip
> power-domain regulator handling manage the GPU domain supply.
>
> A corresponding domain-supply property is needed in the board DT.
>
> The regulator-capable descriptors are based on the regulator support in
> Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
> delay changes.
>
> Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
> Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
> Signed-off-by: Leonard Lausen <leonard@lausen.nl>
So this should be applied as a fix and tagged for stable kernels, right?
Kind regards
Uffe
>
> ---
> drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index e193f978d5f35..b41f9fcb62bfe 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
> @@ -176,41 +176,42 @@ struct rockchip_pmu {
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> .need_regulator = regulator, \
> }
>
> -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
> +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_offset = p_offset, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .clk_ungate_mask = (g_mask), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> + .need_regulator = regulator, \
> }
>
> #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> @@ -250,25 +251,28 @@ struct rockchip_pmu {
> DOMAIN(name, pwr, status, req, req, req, wakeup)
>
> #define DOMAIN_RK3528(name, pwr, req) \
> DOMAIN_M(name, pwr, pwr, req, req, req, false)
>
> #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
> DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
>
> #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
> DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
>
> #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, false)
> +
> +#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, true)
>
> /*
> * Dynamic Memory Controller may need to coordinate with us -- see
> * rockchip_pmu_block().
> *
> * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
> * block() while we're initializing the PMU.
> */
> static DEFINE_MUTEX(dmc_pmu_mutex);
> static struct rockchip_pmu *dmc_pmu;
>
> /*
> @@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
> [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
> [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
> [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
> [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
> [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
> [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
> [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
> [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
> [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
> [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
> [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
> - [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> + [RK3576_PD_GPU] = DOMAIN_RK3576_R("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> };
>
> static const struct rockchip_domain_info rk3588_pm_domains[] = {
> [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
> [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
> [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
> --
> 2.47.3
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-11-12 15:19 ` Ulf Hansson
@ 2026-11-12 16:10 ` Leonard Lausen
2026-11-12 18:15 ` Sebastian Reichel
1 sibling, 0 replies; 8+ messages in thread
From: Leonard Lausen @ 2026-11-12 16:10 UTC (permalink / raw)
To: Ulf Hansson
Cc: ulfh, heiko, robh, krzk+dt, conor+dt, detlev.casanova,
finley.xiao, zhangqing, inindev, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-pm, gahing
Am 12.11.26 um 16:19 schrieb Ulf Hansson:
> On Mon, Oct 19, 2026 at 11:24 AM Leonard Lausen <leonard@lausen.nl> wrote:
>>
>> On the NanoPi M5, boot hangs during Panfrost initialization. Before this
>> fix, booting required blacklisting Panfrost on the kernel command line.
>> Loading Panfrost after boot reports a GPU power-domain acknowledgment
>> timeout:
>>
>> failed to get ack on domain 'gpu', val=0x113ff
>>
>> Add regulator support to the RK3576 domain descriptors and mark the GPU
>> domain as regulator-dependent. This lets the existing Rockchip
>> power-domain regulator handling manage the GPU domain supply.
>>
>> A corresponding domain-supply property is needed in the board DT.
>>
>> The regulator-capable descriptors are based on the regulator support in
>> Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
>> delay changes.
>>
>> Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
>> Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
>> Signed-off-by: Leonard Lausen <leonard@lausen.nl>
>
> So this should be applied as a fix and tagged for stable kernels, right?
Hi Uffe,
No concerns on backporting from my side. I was previously running 6.19
and had to disable panfrost to avoid the boot hang fixed here. I
validated the fix only on 7.3 however. If you prefer only applying to
next, it also works for me.
Best regards
Leonard
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
2026-10-19 10:05 ` Shawn Lin
2026-11-12 15:19 ` Ulf Hansson
@ 2026-11-12 18:12 ` Sebastian Reichel
2 siblings, 0 replies; 8+ messages in thread
From: Sebastian Reichel @ 2026-11-12 18:12 UTC (permalink / raw)
To: Leonard Lausen
Cc: ulfh, heiko, robh, krzk+dt, conor+dt, detlev.casanova,
finley.xiao, zhangqing, inindev, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-pm, gahing
[-- Attachment #1: Type: text/plain, Size: 7571 bytes --]
Hi,
On Mon, Oct 19, 2026 at 09:24:15AM +0000, Leonard Lausen wrote:
> On the NanoPi M5, boot hangs during Panfrost initialization. Before this
> fix, booting required blacklisting Panfrost on the kernel command line.
> Loading Panfrost after boot reports a GPU power-domain acknowledgment
> timeout:
>
> failed to get ack on domain 'gpu', val=0x113ff
>
> Add regulator support to the RK3576 domain descriptors and mark the GPU
> domain as regulator-dependent. This lets the existing Rockchip
> power-domain regulator handling manage the GPU domain supply.
>
> A corresponding domain-supply property is needed in the board DT.
>
> The regulator-capable descriptors are based on the regulator support in
> Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
> delay changes.
>
> Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
> Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
> Signed-off-by: Leonard Lausen <leonard@lausen.nl>
> ---
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Greetings,
-- Sebastian
> drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> index e193f978d5f35..b41f9fcb62bfe 100644
> --- a/drivers/pmdomain/rockchip/pm-domains.c
> +++ b/drivers/pmdomain/rockchip/pm-domains.c
> @@ -176,41 +176,42 @@ struct rockchip_pmu {
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> .need_regulator = regulator, \
> }
>
> -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
> +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_offset = p_offset, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .mem_offset = m_offset, \
> .mem_status_mask = (m_status), \
> .repair_status_mask = (r_status), \
> .req_offset = r_offset, \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .clk_ungate_mask = (g_mask), \
> .ack_mask = (ack), \
> .active_wakeup = wakeup, \
> + .need_regulator = regulator, \
> }
>
> #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
> { \
> .name = _name, \
> .pwr_w_mask = (pwr) << 16, \
> .pwr_mask = (pwr), \
> .status_mask = (status), \
> .req_w_mask = (req) << 16, \
> .req_mask = (req), \
> .idle_mask = (idle), \
> .ack_mask = (ack), \
> @@ -250,25 +251,28 @@ struct rockchip_pmu {
> DOMAIN(name, pwr, status, req, req, req, wakeup)
>
> #define DOMAIN_RK3528(name, pwr, req) \
> DOMAIN_M(name, pwr, pwr, req, req, req, false)
>
> #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
> DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
>
> #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
> DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
>
> #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, false)
> +
> +#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, true)
>
> /*
> * Dynamic Memory Controller may need to coordinate with us -- see
> * rockchip_pmu_block().
> *
> * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
> * block() while we're initializing the PMU.
> */
> static DEFINE_MUTEX(dmc_pmu_mutex);
> static struct rockchip_pmu *dmc_pmu;
>
> /*
> @@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
> [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
> [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
> [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
> [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
> [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
> [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
> [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
> [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
> [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
> [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
> [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
> - [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> + [RK3576_PD_GPU] = DOMAIN_RK3576_R("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> };
>
> static const struct rockchip_domain_info rk3588_pm_domains[] = {
> [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
> [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
> [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
> --
> 2.47.3
>
>
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* Re: [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply
2026-11-12 15:19 ` Ulf Hansson
2026-11-12 16:10 ` Leonard Lausen
@ 2026-11-12 18:15 ` Sebastian Reichel
1 sibling, 0 replies; 8+ messages in thread
From: Sebastian Reichel @ 2026-11-12 18:15 UTC (permalink / raw)
To: Ulf Hansson
Cc: Leonard Lausen, ulfh, heiko, robh, krzk+dt, conor+dt,
detlev.casanova, finley.xiao, zhangqing, inindev, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, linux-pm, gahing
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Hi,
On Thu, Nov 12, 2026 at 04:19:58PM +0100, Ulf Hansson wrote:
> On Mon, Oct 19, 2026 at 11:24 AM Leonard Lausen <leonard@lausen.nl> wrote:
> >
> > On the NanoPi M5, boot hangs during Panfrost initialization. Before this
> > fix, booting required blacklisting Panfrost on the kernel command line.
> > Loading Panfrost after boot reports a GPU power-domain acknowledgment
> > timeout:
> >
> > failed to get ack on domain 'gpu', val=0x113ff
> >
> > Add regulator support to the RK3576 domain descriptors and mark the GPU
> > domain as regulator-dependent. This lets the existing Rockchip
> > power-domain regulator handling manage the GPU domain supply.
> >
> > A corresponding domain-supply property is needed in the board DT.
> >
> > The regulator-capable descriptors are based on the regulator support in
> > Jiaxing Hu's pending RK3576 NPU enablement series, without its NPU settle
> > delay changes.
> >
> > Link: https://lore.kernel.org/all/20260924102135.92217-10-gahing@gahingwoo.com/
> > Fixes: cfee1b507758 ("pmdomain: rockchip: Add support for RK3576 SoC")
> > Signed-off-by: Leonard Lausen <leonard@lausen.nl>
>
> So this should be applied as a fix and tagged for stable kernels, right?
Maybe like this, considering it requires regulator support, which
landed in db6df2e3fc16 ("pmdomain: rockchip: add regulator
support"):
Cc: stable@vger.kernel.org # v6.15+
Greetings,
-- Sebastian
>
> Kind regards
> Uffe
>
> >
> > ---
> > drivers/pmdomain/rockchip/pm-domains.c | 10 +++++++---
> > 1 file changed, 7 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c
> > index e193f978d5f35..b41f9fcb62bfe 100644
> > --- a/drivers/pmdomain/rockchip/pm-domains.c
> > +++ b/drivers/pmdomain/rockchip/pm-domains.c
> > @@ -176,41 +176,42 @@ struct rockchip_pmu {
> > .mem_offset = m_offset, \
> > .mem_status_mask = (m_status), \
> > .repair_status_mask = (r_status), \
> > .req_offset = r_offset, \
> > .req_w_mask = (req) << 16, \
> > .req_mask = (req), \
> > .idle_mask = (idle), \
> > .ack_mask = (ack), \
> > .active_wakeup = wakeup, \
> > .need_regulator = regulator, \
> > }
> >
> > -#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
> > +#define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup, regulator) \
> > { \
> > .name = _name, \
> > .pwr_offset = p_offset, \
> > .pwr_w_mask = (pwr) << 16, \
> > .pwr_mask = (pwr), \
> > .status_mask = (status), \
> > .mem_offset = m_offset, \
> > .mem_status_mask = (m_status), \
> > .repair_status_mask = (r_status), \
> > .req_offset = r_offset, \
> > .req_w_mask = (req) << 16, \
> > .req_mask = (req), \
> > .idle_mask = (idle), \
> > .clk_ungate_mask = (g_mask), \
> > .ack_mask = (ack), \
> > .active_wakeup = wakeup, \
> > + .need_regulator = regulator, \
> > }
> >
> > #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
> > { \
> > .name = _name, \
> > .pwr_w_mask = (pwr) << 16, \
> > .pwr_mask = (pwr), \
> > .status_mask = (status), \
> > .req_w_mask = (req) << 16, \
> > .req_mask = (req), \
> > .idle_mask = (idle), \
> > .ack_mask = (ack), \
> > @@ -250,25 +251,28 @@ struct rockchip_pmu {
> > DOMAIN(name, pwr, status, req, req, req, wakeup)
> >
> > #define DOMAIN_RK3528(name, pwr, req) \
> > DOMAIN_M(name, pwr, pwr, req, req, req, false)
> >
> > #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
> > DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
> >
> > #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
> > DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
> >
> > #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> > - DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
> > + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, false)
> > +
> > +#define DOMAIN_RK3576_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
> > + DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup, true)
> >
> > /*
> > * Dynamic Memory Controller may need to coordinate with us -- see
> > * rockchip_pmu_block().
> > *
> > * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
> > * block() while we're initializing the PMU.
> > */
> > static DEFINE_MUTEX(dmc_pmu_mutex);
> > static struct rockchip_pmu *dmc_pmu;
> >
> > /*
> > @@ -1323,25 +1327,25 @@ static const struct rockchip_domain_info rk3576_pm_domains[] = {
> > [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
> > [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
> > [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
> > [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
> > [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
> > [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
> > [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
> > [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
> > [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
> > [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
> > [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
> > [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
> > - [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> > + [RK3576_PD_GPU] = DOMAIN_RK3576_R("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
> > };
> >
> > static const struct rockchip_domain_info rk3588_pm_domains[] = {
> > [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
> > [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
> > [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
> > [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
> > [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
> > [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
> > [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
> > [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
> > [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
> > --
> > 2.47.3
> >
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-11-12 18:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-19 9:24 [PATCH 0/2] Fix Panfrost boot hang on NanoPi M5 Leonard Lausen
2026-10-19 9:24 ` [PATCH 1/2] pmdomain: rockchip: Manage the RK3576 GPU domain supply Leonard Lausen
2026-10-19 10:05 ` Shawn Lin
2026-11-12 15:19 ` Ulf Hansson
2026-11-12 16:10 ` Leonard Lausen
2026-11-12 18:15 ` Sebastian Reichel
2026-11-12 18:12 ` Sebastian Reichel
2026-10-19 9:24 ` [PATCH 2/2] arm64: dts: rockchip: Fix GPU domain supply on NanoPi M5 Leonard Lausen
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