[PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards

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* [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards
@ 2026-01-08 17:15 Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
                   ` (5 more replies)
  0 siblings, 6 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:15 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.
    
To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
Changes in v3:
- Remove duplicate bootph-all property in ltdc node
- Link to v2: https://lore.kernel.org/r/20251114-upstream_uboot_properties-v2-0-3784ff668ae0@foss.st.com

Changes in v2:
- Fix 'pinmux' is a required property for arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dtb
- Add bootph-all property for lvds and ltdc nodes for stm32mp2

---
Patrice Chotard (6):
      ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards
      ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards
      ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards
      ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards
      ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
      arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards

 arch/arm/boot/dts/st/stm32429i-eval.dts       | 11 +++++
 arch/arm/boot/dts/st/stm32746g-eval.dts       | 10 +++++
 arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi     | 12 ++++++
 arch/arm/boot/dts/st/stm32f429-disco.dts      | 11 +++++
 arch/arm/boot/dts/st/stm32f429.dtsi           |  9 ++++
 arch/arm/boot/dts/st/stm32f469-disco.dts      | 12 ++++++
 arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi     | 11 +++++
 arch/arm/boot/dts/st/stm32f746-disco.dts      | 12 ++++++
 arch/arm/boot/dts/st/stm32f746.dtsi           |  5 +++
 arch/arm/boot/dts/st/stm32f769-disco.dts      | 12 ++++++
 arch/arm/boot/dts/st/stm32h743.dtsi           | 19 +++++++++
 arch/arm/boot/dts/st/stm32mp131.dtsi          | 21 ++++++++++
 arch/arm/boot/dts/st/stm32mp135f-dk.dts       | 11 +++++
 arch/arm/boot/dts/st/stm32mp15-scmi.dtsi      | 26 ++++++++++++
 arch/arm/boot/dts/st/stm32mp151.dtsi          | 29 +++++++++++++
 arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++
 arch/arm/boot/dts/st/stm32mp157a-dk1.dts      | 43 +++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-dk2.dts      | 43 +++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++
 arch/arm/boot/dts/st/stm32mp157c-ed1.dts      | 60 +++++++++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 25 +++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ev1.dts      | 36 ++++++++++++++++
 arch/arm64/boot/dts/st/stm32mp211.dtsi        |  7 ++++
 arch/arm64/boot/dts/st/stm32mp215f-dk.dts     |  1 +
 arch/arm64/boot/dts/st/stm32mp231.dtsi        | 22 ++++++++++
 arch/arm64/boot/dts/st/stm32mp235f-dk.dts     | 11 +++++
 arch/arm64/boot/dts/st/stm32mp251.dtsi        | 25 +++++++++++
 arch/arm64/boot/dts/st/stm32mp255.dtsi        |  3 +-
 arch/arm64/boot/dts/st/stm32mp257f-dk.dts     | 11 +++++
 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts    | 11 +++++
 30 files changed, 536 insertions(+), 1 deletion(-)
---
base-commit: 53c18dc078bb6d9e9dfe2cc0671ab78588c44723
change-id: 20251112-upstream_uboot_properties-22480b0b4b1c

Best regards,
-- 
Patrice Chotard <patrice.chotard@foss.st.com>


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32429i-eval.dts   | 11 +++++++++++
 arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi | 12 ++++++++++++
 arch/arm/boot/dts/st/stm32f429-disco.dts  | 11 +++++++++++
 arch/arm/boot/dts/st/stm32f429.dtsi       |  9 +++++++++
 arch/arm/boot/dts/st/stm32f469-disco.dts  | 12 ++++++++++++
 5 files changed, 55 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32429i-eval.dts b/arch/arm/boot/dts/st/stm32429i-eval.dts
index afa417b34b25..3b6151fcb070 100644
--- a/arch/arm/boot/dts/st/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/st/stm32429i-eval.dts
@@ -312,6 +312,7 @@ &timers5 {
 	/* Override timer5 to act as clockevent */
 	compatible = "st,stm32-timer";
 	interrupts = <50>;
+	bootph-all;
 	status = "okay";
 	/delete-property/#address-cells;
 	/delete-property/#size-cells;
@@ -326,6 +327,16 @@ &usart1 {
 	status = "okay";
 };
 
+&usart1_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_hs {
 	dr_mode = "host";
 	phys = <&usbotg_hs_phy>;
diff --git a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
index 3bb812d6399e..bcaed4618738 100644
--- a/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32f4-pinctrl.dtsi
@@ -51,6 +51,7 @@ pinctrl: pinctrl@40020000 {
 			ranges = <0 0x40020000 0x3000>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&syscfg 0x8>;
+			bootph-all;
 
 			gpioa: gpio@40020000 {
 				gpio-controller;
@@ -60,6 +61,7 @@ gpioa: gpio@40020000 {
 				reg = <0x0 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
 				st,bank-name = "GPIOA";
+				bootph-all;
 			};
 
 			gpiob: gpio@40020400 {
@@ -70,6 +72,7 @@ gpiob: gpio@40020400 {
 				reg = <0x400 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
 				st,bank-name = "GPIOB";
+				bootph-all;
 			};
 
 			gpioc: gpio@40020800 {
@@ -80,6 +83,7 @@ gpioc: gpio@40020800 {
 				reg = <0x800 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
 				st,bank-name = "GPIOC";
+				bootph-all;
 			};
 
 			gpiod: gpio@40020c00 {
@@ -90,6 +94,7 @@ gpiod: gpio@40020c00 {
 				reg = <0xc00 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
 				st,bank-name = "GPIOD";
+				bootph-all;
 			};
 
 			gpioe: gpio@40021000 {
@@ -100,6 +105,7 @@ gpioe: gpio@40021000 {
 				reg = <0x1000 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
 				st,bank-name = "GPIOE";
+				bootph-all;
 			};
 
 			gpiof: gpio@40021400 {
@@ -110,6 +116,7 @@ gpiof: gpio@40021400 {
 				reg = <0x1400 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
 				st,bank-name = "GPIOF";
+				bootph-all;
 			};
 
 			gpiog: gpio@40021800 {
@@ -120,6 +127,7 @@ gpiog: gpio@40021800 {
 				reg = <0x1800 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
 				st,bank-name = "GPIOG";
+				bootph-all;
 			};
 
 			gpioh: gpio@40021c00 {
@@ -130,6 +138,7 @@ gpioh: gpio@40021c00 {
 				reg = <0x1c00 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
 				st,bank-name = "GPIOH";
+				bootph-all;
 			};
 
 			gpioi: gpio@40022000 {
@@ -140,6 +149,7 @@ gpioi: gpio@40022000 {
 				reg = <0x2000 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
 				st,bank-name = "GPIOI";
+				bootph-all;
 			};
 
 			gpioj: gpio@40022400 {
@@ -150,6 +160,7 @@ gpioj: gpio@40022400 {
 				reg = <0x2400 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
 				st,bank-name = "GPIOJ";
+				bootph-all;
 			};
 
 			gpiok: gpio@40022800 {
@@ -160,6 +171,7 @@ gpiok: gpio@40022800 {
 				reg = <0x2800 0x400>;
 				clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
 				st,bank-name = "GPIOK";
+				bootph-all;
 			};
 
 			usart1_pins_a: usart1-0 {
diff --git a/arch/arm/boot/dts/st/stm32f429-disco.dts b/arch/arm/boot/dts/st/stm32f429-disco.dts
index a3cb4aabdd5a..39a80a9caa5f 100644
--- a/arch/arm/boot/dts/st/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f429-disco.dts
@@ -209,6 +209,7 @@ &timers5 {
 	/* Override timer5 to act as clockevent */
 	compatible = "st,stm32-timer";
 	interrupts = <50>;
+	bootph-all;
 	status = "okay";
 	/delete-property/#address-cells;
 	/delete-property/#size-cells;
@@ -223,6 +224,16 @@ &usart1 {
 	status = "okay";
 };
 
+&usart1_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_hs {
 	compatible = "st,stm32f4x9-fsotg";
 	dr_mode = "host";
diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi
index ad91b74ddd0d..51c931f7b9d5 100644
--- a/arch/arm/boot/dts/st/stm32f429.dtsi
+++ b/arch/arm/boot/dts/st/stm32f429.dtsi
@@ -54,16 +54,20 @@ / {
 	#size-cells = <1>;
 
 	clocks {
+		bootph-all;
+
 		clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
+			bootph-all;
 		};
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			bootph-all;
 		};
 
 		clk_lsi: clk-lsi {
@@ -76,10 +80,12 @@ clk_i2s_ckin: i2s-ckin {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
+			bootph-all;
 		};
 	};
 
 	soc {
+		bootph-all;
 		romem: efuse@1fff7800 {
 			compatible = "st,stm32f4-otp";
 			reg = <0x1fff7800 0x400>;
@@ -580,6 +586,7 @@ syscfg: syscon@40013800 {
 			compatible = "st,stm32-syscfg", "syscon";
 			reg = <0x40013800 0x400>;
 			clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
+			bootph-all;
 		};
 
 		exti: interrupt-controller@40013c00 {
@@ -666,6 +673,7 @@ spi6: spi@40015400 {
 		pwrcfg: power-config@40007000 {
 			compatible = "st,stm32-power-config", "syscon";
 			reg = <0x40007000 0x400>;
+			bootph-all;
 		};
 
 		ltdc: display-controller@40016800 {
@@ -694,6 +702,7 @@ rcc: rcc@40023800 {
 			st,syscfg = <&pwrcfg>;
 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 			assigned-clock-rates = <1000000>;
+			bootph-all;
 		};
 
 		dma1: dma-controller@40026000 {
diff --git a/arch/arm/boot/dts/st/stm32f469-disco.dts b/arch/arm/boot/dts/st/stm32f469-disco.dts
index 8a4f8ddd083d..de025a385e9e 100644
--- a/arch/arm/boot/dts/st/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f469-disco.dts
@@ -169,6 +169,7 @@ dsi_panel_in: endpoint {
 };
 
 &ltdc {
+	bootph-all;
 	status = "okay";
 
 	port {
@@ -225,6 +226,7 @@ &timers5 {
 	/* Override timer5 to act as clockevent */
 	compatible = "st,stm32-timer";
 	interrupts = <50>;
+	bootph-all;
 	status = "okay";
 	/delete-property/#address-cells;
 	/delete-property/#size-cells;
@@ -239,6 +241,16 @@ &usart3 {
 	status = "okay";
 };
 
+&usart3_pins_a	{
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_fs {
 	dr_mode = "host";
 	pinctrl-0 = <&usbotg_fs_pins_a>;

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32746g-eval.dts   | 10 ++++++++++
 arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi | 11 +++++++++++
 arch/arm/boot/dts/st/stm32f746-disco.dts  | 12 ++++++++++++
 arch/arm/boot/dts/st/stm32f746.dtsi       |  5 +++++
 arch/arm/boot/dts/st/stm32f769-disco.dts  | 12 ++++++++++++
 5 files changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32746g-eval.dts b/arch/arm/boot/dts/st/stm32746g-eval.dts
index e9ac37b6eca0..26c5796a81fb 100644
--- a/arch/arm/boot/dts/st/stm32746g-eval.dts
+++ b/arch/arm/boot/dts/st/stm32746g-eval.dts
@@ -213,6 +213,16 @@ &usart1 {
 	status = "okay";
 };
 
+&usart1_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_hs {
 	dr_mode = "otg";
 	phys = <&usbotg_hs_phy>;
diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
index 97fc3fb5a9ca..6b01c3c84272 100644
--- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
+++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi
@@ -24,6 +24,7 @@ gpioa: gpio@40020000 {
 				reg = <0x0 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
 				st,bank-name = "GPIOA";
+				bootph-all;
 			};
 
 			gpiob: gpio@40020400 {
@@ -34,6 +35,7 @@ gpiob: gpio@40020400 {
 				reg = <0x400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
 				st,bank-name = "GPIOB";
+				bootph-all;
 			};
 
 			gpioc: gpio@40020800 {
@@ -44,6 +46,7 @@ gpioc: gpio@40020800 {
 				reg = <0x800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
 				st,bank-name = "GPIOC";
+				bootph-all;
 			};
 
 			gpiod: gpio@40020c00 {
@@ -54,6 +57,7 @@ gpiod: gpio@40020c00 {
 				reg = <0xc00 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
 				st,bank-name = "GPIOD";
+				bootph-all;
 			};
 
 			gpioe: gpio@40021000 {
@@ -64,6 +68,7 @@ gpioe: gpio@40021000 {
 				reg = <0x1000 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
 				st,bank-name = "GPIOE";
+				bootph-all;
 			};
 
 			gpiof: gpio@40021400 {
@@ -74,6 +79,7 @@ gpiof: gpio@40021400 {
 				reg = <0x1400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
 				st,bank-name = "GPIOF";
+				bootph-all;
 			};
 
 			gpiog: gpio@40021800 {
@@ -84,6 +90,7 @@ gpiog: gpio@40021800 {
 				reg = <0x1800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
 				st,bank-name = "GPIOG";
+				bootph-all;
 			};
 
 			gpioh: gpio@40021c00 {
@@ -94,6 +101,7 @@ gpioh: gpio@40021c00 {
 				reg = <0x1c00 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
 				st,bank-name = "GPIOH";
+				bootph-all;
 			};
 
 			gpioi: gpio@40022000 {
@@ -104,6 +112,7 @@ gpioi: gpio@40022000 {
 				reg = <0x2000 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
 				st,bank-name = "GPIOI";
+				bootph-all;
 			};
 
 			gpioj: gpio@40022400 {
@@ -114,6 +123,7 @@ gpioj: gpio@40022400 {
 				reg = <0x2400 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
 				st,bank-name = "GPIOJ";
+				bootph-all;
 			};
 
 			gpiok: gpio@40022800 {
@@ -124,6 +134,7 @@ gpiok: gpio@40022800 {
 				reg = <0x2800 0x400>;
 				clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
 				st,bank-name = "GPIOK";
+				bootph-all;
 			};
 
 			cec_pins_a: cec-0 {
diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts
index b57dbdce2f40..9545b14d77c3 100644
--- a/arch/arm/boot/dts/st/stm32f746-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f746-disco.dts
@@ -169,6 +169,7 @@ touchscreen@38 {
 &ltdc {
 	pinctrl-0 = <&ltdc_pins_a>;
 	pinctrl-names = "default";
+	bootph-all;
 	status = "okay";
 
 	port {
@@ -207,6 +208,17 @@ &usart1 {
 	status = "okay";
 };
 
+
+&usart1_pins_b {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_fs {
 	dr_mode = "host";
 	pinctrl-0 = <&usbotg_fs_pins_a>;
diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi
index 208f8c6dfc9d..b0f012de759c 100644
--- a/arch/arm/boot/dts/st/stm32f746.dtsi
+++ b/arch/arm/boot/dts/st/stm32f746.dtsi
@@ -54,6 +54,7 @@ clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
+			bootph-all;
 		};
 
 		clk-lse {
@@ -76,6 +77,7 @@ clk_i2s_ckin: clk-i2s-ckin {
 	};
 
 	soc {
+		bootph-all;
 		timers2: timers@40000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -149,6 +151,7 @@ timers5: timers@40000c00 {
 			reg = <0x40000C00 0x400>;
 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
 			clock-names = "int";
+			bootph-all;
 			status = "disabled";
 
 			pwm {
@@ -645,6 +648,7 @@ ltdc: display-controller@40016800 {
 		pwrcfg: power-config@40007000 {
 			compatible = "st,stm32-power-config", "syscon";
 			reg = <0x40007000 0x400>;
+			bootph-all;
 		};
 
 		crc: crc@40023000 {
@@ -663,6 +667,7 @@ rcc: rcc@40023800 {
 			st,syscfg = <&pwrcfg>;
 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 			assigned-clock-rates = <1000000>;
+			bootph-all;
 		};
 
 		dma1: dma-controller@40026000 {
diff --git a/arch/arm/boot/dts/st/stm32f769-disco.dts b/arch/arm/boot/dts/st/stm32f769-disco.dts
index 535cfdc4681c..539517c7991e 100644
--- a/arch/arm/boot/dts/st/stm32f769-disco.dts
+++ b/arch/arm/boot/dts/st/stm32f769-disco.dts
@@ -133,6 +133,7 @@ &clk_hse {
 &dsi {
 	#address-cells = <1>;
 	#size-cells = <0>;
+	bootph-all;
 	status = "okay";
 
 	ports {
@@ -178,6 +179,7 @@ &i2c1 {
 };
 
 &ltdc {
+	bootph-all;
 	status = "okay";
 
 	port {
@@ -221,6 +223,16 @@ &usart1 {
 	status = "okay";
 };
 
+&usart1_pins_a	{
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_hs {
 	dr_mode = "otg";
 	phys = <&usbotg_hs_phy>;

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32h743.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi
index 2f19cfbc57ad..790e4558c905 100644
--- a/arch/arm/boot/dts/st/stm32h743.dtsi
+++ b/arch/arm/boot/dts/st/stm32h743.dtsi
@@ -50,22 +50,26 @@ / {
 	#size-cells = <1>;
 
 	clocks {
+		bootph-all;
 		clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
+			bootph-all;
 		};
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			bootph-all;
 		};
 
 		clk_i2s: i2s_ckin {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <0>;
+			bootph-all;
 		};
 	};
 
@@ -75,6 +79,7 @@ timer5: timer@40000c00 {
 			reg = <0x40000c00 0x400>;
 			interrupts = <50>;
 			clocks = <&rcc TIM5_CK>;
+			bootph-all;
 		};
 
 		lptimer1: timer@40002400 {
@@ -547,11 +552,13 @@ rcc: reset-clock-controller@58024400 {
 			#reset-cells = <1>;
 			clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
 			st,syscfg = <&pwrcfg>;
+			bootph-all;
 		};
 
 		pwrcfg: power-config@58024800 {
 			compatible = "st,stm32-power-config", "syscon";
 			reg = <0x58024800 0x400>;
+			bootph-all;
 		};
 
 		adc_3: adc@58026000 {
@@ -596,6 +603,7 @@ pinctrl: pinctrl@58020000 {
 			ranges = <0 0x58020000 0x3000>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&syscfg 0x8>;
+			bootph-all;
 
 			gpioa: gpio@58020000 {
 				gpio-controller;
@@ -607,6 +615,7 @@ gpioa: gpio@58020000 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 0 16>;
+				bootph-all;
 			};
 
 			gpiob: gpio@58020400 {
@@ -619,6 +628,7 @@ gpiob: gpio@58020400 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 16 16>;
+				bootph-all;
 			};
 
 			gpioc: gpio@58020800 {
@@ -631,6 +641,7 @@ gpioc: gpio@58020800 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 32 16>;
+				bootph-all;
 			};
 
 			gpiod: gpio@58020c00 {
@@ -643,6 +654,7 @@ gpiod: gpio@58020c00 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 48 16>;
+				bootph-all;
 			};
 
 			gpioe: gpio@58021000 {
@@ -655,6 +667,7 @@ gpioe: gpio@58021000 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 64 16>;
+				bootph-all;
 			};
 
 			gpiof: gpio@58021400 {
@@ -667,6 +680,7 @@ gpiof: gpio@58021400 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 80 16>;
+				bootph-all;
 			};
 
 			gpiog: gpio@58021800 {
@@ -679,6 +693,7 @@ gpiog: gpio@58021800 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 96 16>;
+				bootph-all;
 			};
 
 			gpioh: gpio@58021c00 {
@@ -691,6 +706,7 @@ gpioh: gpio@58021c00 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 112 16>;
+				bootph-all;
 			};
 
 			gpioi: gpio@58022000 {
@@ -703,6 +719,7 @@ gpioi: gpio@58022000 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 128 16>;
+				bootph-all;
 			};
 
 			gpioj: gpio@58022400 {
@@ -715,6 +732,7 @@ gpioj: gpio@58022400 {
 				#interrupt-cells = <2>;
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 144 16>;
+				bootph-all;
 			};
 
 			gpiok: gpio@58022800 {
@@ -727,6 +745,7 @@ gpiok: gpio@58022800 {
 				#interrupt-cells = <2>;
 				ngpios = <8>;
 				gpio-ranges = <&pinctrl 0 160 8>;
+				bootph-all;
 			};
 		};
 	};

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
                   ` (2 preceding siblings ...)
  2026-01-08 17:16 ` [PATCH v3 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard
  2026-01-08 17:16 ` [PATCH v3 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard
  5 siblings, 0 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp131.dtsi    | 21 +++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp135f-dk.dts | 11 +++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index fd730aa37c22..26c3b5529582 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
@@ -35,6 +35,7 @@ optee {
 			compatible = "linaro,optee-tz";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+			bootph-all;
 		};
 
 		scmi: scmi {
@@ -42,15 +43,18 @@ scmi: scmi {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
+			bootph-all;
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_voltd: protocol@17 {
@@ -88,6 +92,7 @@ intc: interrupt-controller@a0021000 {
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+		bootph-some-ram;
 	};
 
 	timer {
@@ -131,6 +136,7 @@ soc {
 		#size-cells = <1>;
 		interrupt-parent = <&intc>;
 		ranges;
+		bootph-all;
 
 		timers2: timer@40000000 {
 			#address-cells = <1>;
@@ -791,6 +797,7 @@ rcc: rcc@50000000 {
 				 <&scmi_clk CK_SCMI_CSI>,
 				 <&scmi_clk CK_SCMI_LSE>,
 				 <&scmi_clk CK_SCMI_LSI>;
+			bootph-all;
 		};
 
 		pwr_regulators: pwr@50001000 {
@@ -900,6 +907,7 @@ syscfg: syscon@50020000 {
 			compatible = "st,stm32mp157-syscfg", "syscon";
 			reg = <0x50020000 0x400>;
 			clocks = <&rcc SYSCFG>;
+			bootph-all;
 		};
 
 		lptimer4: timer@50023000 {
@@ -1003,6 +1011,7 @@ iwdg2: watchdog@5a002000 {
 			clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
 			clock-names = "pclk", "lsi";
 			status = "disabled";
+			bootph-all;
 		};
 
 		rtc: rtc@5c004000 {
@@ -1020,6 +1029,7 @@ bsec: efuse@5c005000 {
 			reg = <0x5c005000 0x400>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			bootph-all;
 
 			part_number_otp: part_number_otp@4 {
 				reg = <0x4 0x2>;
@@ -1646,6 +1656,7 @@ usbphyc: usbphyc@5a006000 {
 				vdda1v8-supply = <&scmi_reg18>;
 				access-controllers = <&etzpc 5>;
 				status = "disabled";
+				bootph-all;
 
 				usbphyc_port0: usb-phy@0 {
 					#phy-cells = <0>;
@@ -1670,6 +1681,7 @@ pinctrl: pinctrl@50002000 {
 			ranges = <0 0x50002000 0x8400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
+			bootph-all;
 
 			gpioa: gpio@50002000 {
 				gpio-controller;
@@ -1681,6 +1693,7 @@ gpioa: gpio@50002000 {
 				st,bank-name = "GPIOA";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 0 16>;
+				bootph-all;
 			};
 
 			gpiob: gpio@50003000 {
@@ -1693,6 +1706,7 @@ gpiob: gpio@50003000 {
 				st,bank-name = "GPIOB";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 16 16>;
+				bootph-all;
 			};
 
 			gpioc: gpio@50004000 {
@@ -1705,6 +1719,7 @@ gpioc: gpio@50004000 {
 				st,bank-name = "GPIOC";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 32 16>;
+				bootph-all;
 			};
 
 			gpiod: gpio@50005000 {
@@ -1717,6 +1732,7 @@ gpiod: gpio@50005000 {
 				st,bank-name = "GPIOD";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 48 16>;
+				bootph-all;
 			};
 
 			gpioe: gpio@50006000 {
@@ -1729,6 +1745,7 @@ gpioe: gpio@50006000 {
 				st,bank-name = "GPIOE";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 64 16>;
+				bootph-all;
 			};
 
 			gpiof: gpio@50007000 {
@@ -1741,6 +1758,7 @@ gpiof: gpio@50007000 {
 				st,bank-name = "GPIOF";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 80 16>;
+				bootph-all;
 			};
 
 			gpiog: gpio@50008000 {
@@ -1753,6 +1771,7 @@ gpiog: gpio@50008000 {
 				st,bank-name = "GPIOG";
 				ngpios = <16>;
 				gpio-ranges = <&pinctrl 0 96 16>;
+				bootph-all;
 			};
 
 			gpioh: gpio@50009000 {
@@ -1765,6 +1784,7 @@ gpioh: gpio@50009000 {
 				st,bank-name = "GPIOH";
 				ngpios = <15>;
 				gpio-ranges = <&pinctrl 0 112 15>;
+				bootph-all;
 			};
 
 			gpioi: gpio@5000a000 {
@@ -1777,6 +1797,7 @@ gpioi: gpio@5000a000 {
 				st,bank-name = "GPIOI";
 				ngpios = <8>;
 				gpio-ranges = <&pinctrl 0 128 8>;
+				bootph-all;
 			};
 		};
 	};
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 9764a6bfa5b4..a05d458c9b37 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
@@ -517,9 +517,20 @@ &uart4 {
 	pinctrl-2 = <&uart4_idle_pins_a>;
 	/delete-property/dmas;
 	/delete-property/dma-names;
+	bootph-all;
 	status = "okay";
 };
 
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &uart8 {
 	pinctrl-names = "default", "sleep", "idle";
 	pinctrl-0 = <&uart8_pins_a>;

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
                   ` (3 preceding siblings ...)
  2026-01-08 17:16 ` [PATCH v3 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  2026-01-09  8:19   ` Alexandre TORGUE
  2026-01-08 17:16 ` [PATCH v3 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard
  5 siblings, 1 reply; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm/boot/dts/st/stm32mp15-scmi.dtsi      | 26 ++++++++++++
 arch/arm/boot/dts/st/stm32mp151.dtsi          | 29 +++++++++++++
 arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++
 arch/arm/boot/dts/st/stm32mp157a-dk1.dts      | 43 +++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-dk2.dts      | 43 +++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++
 arch/arm/boot/dts/st/stm32mp157c-ed1.dts      | 60 +++++++++++++++++++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 25 +++++++++++
 arch/arm/boot/dts/st/stm32mp157c-ev1.dts      | 36 ++++++++++++++++
 9 files changed, 290 insertions(+)

diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
index 98552fe45d4e..c58d81f505be 100644
--- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
@@ -13,6 +13,7 @@ optee: optee {
 			method = "smc";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+			bootph-some-ram;
 		};
 
 		scmi: scmi {
@@ -20,6 +21,7 @@ scmi: scmi {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
+			bootph-some-ram;
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
@@ -64,6 +66,26 @@ scmi_usb33: regulator@2 {
 	};
 };
 
+&iwdg2 {
+	bootph-all;
+};
+
+&ltdc {
+	bootph-some-ram;
+};
+
+&pinctrl {
+	bootph-all;
+};
+
+&pinctrl_z {
+	bootph-all;
+};
+
+&rcc {
+	bootph-all;
+};
+
 &reg11 {
 	status = "disabled";
 };
@@ -72,6 +94,10 @@ &reg18 {
 	status = "disabled";
 };
 
+&scmi {
+	bootph-some-ram;
+};
+
 &usb33 {
 	status = "disabled";
 };
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index b1b568dfd126..7abee7ce0580 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -33,6 +33,7 @@ arm-pmu {
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+		bootph-some-ram;
 	};
 
 	intc: interrupt-controller@a0021000 {
@@ -54,34 +55,41 @@ timer {
 	};
 
 	clocks {
+		bootph-all;
+
 		clk_hse: clk-hse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <24000000>;
+			bootph-all;
 		};
 
 		clk_hsi: clk-hsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <64000000>;
+			bootph-all;
 		};
 
 		clk_lse: clk-lse {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32768>;
+			bootph-all;
 		};
 
 		clk_lsi: clk-lsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <32000>;
+			bootph-all;
 		};
 
 		clk_csi: clk-csi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <4000000>;
+			bootph-all;
 		};
 	};
 
@@ -122,6 +130,7 @@ soc {
 		#size-cells = <1>;
 		interrupt-parent = <&intc>;
 		ranges;
+		bootph-all;
 
 		ipcc: mailbox@4c001000 {
 			compatible = "st,stm32mp1-ipcc";
@@ -142,11 +151,13 @@ rcc: rcc@50000000 {
 			reg = <0x50000000 0x1000>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
+			bootph-all;
 		};
 
 		pwr_regulators: pwr@50001000 {
 			compatible = "st,stm32mp1,pwr-reg";
 			reg = <0x50001000 0x10>;
+			bootph-all;
 
 			reg11: reg11 {
 				regulator-name = "reg11";
@@ -354,6 +365,7 @@ ltdc: display-controller@5a001000 {
 			clocks = <&rcc LTDC_PX>;
 			clock-names = "lcd";
 			resets = <&rcc LTDC_R>;
+			bootph-some-ram;
 			status = "disabled";
 		};
 
@@ -364,6 +376,7 @@ iwdg2: watchdog@5a002000 {
 			clock-names = "pclk", "lsi";
 			interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>;
 			wakeup-source;
+			bootph-all;
 			status = "disabled";
 		};
 
@@ -404,6 +417,8 @@ bsec: efuse@5c005000 {
 			reg = <0x5c005000 0x400>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			bootph-all;
+
 			part_number_otp: part-number-otp@4 {
 				reg = <0x4 0x1>;
 			};
@@ -1876,6 +1891,7 @@ pinctrl: pinctrl@50002000 {
 			ranges = <0 0x50002000 0xa400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
+			bootph-all;
 
 			gpioa: gpio@50002000 {
 				gpio-controller;
@@ -1885,6 +1901,7 @@ gpioa: gpio@50002000 {
 				reg = <0x0 0x400>;
 				clocks = <&rcc GPIOA>;
 				st,bank-name = "GPIOA";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1896,6 +1913,7 @@ gpiob: gpio@50003000 {
 				reg = <0x1000 0x400>;
 				clocks = <&rcc GPIOB>;
 				st,bank-name = "GPIOB";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1907,6 +1925,7 @@ gpioc: gpio@50004000 {
 				reg = <0x2000 0x400>;
 				clocks = <&rcc GPIOC>;
 				st,bank-name = "GPIOC";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1918,6 +1937,7 @@ gpiod: gpio@50005000 {
 				reg = <0x3000 0x400>;
 				clocks = <&rcc GPIOD>;
 				st,bank-name = "GPIOD";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1929,6 +1949,7 @@ gpioe: gpio@50006000 {
 				reg = <0x4000 0x400>;
 				clocks = <&rcc GPIOE>;
 				st,bank-name = "GPIOE";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1940,6 +1961,7 @@ gpiof: gpio@50007000 {
 				reg = <0x5000 0x400>;
 				clocks = <&rcc GPIOF>;
 				st,bank-name = "GPIOF";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1951,6 +1973,7 @@ gpiog: gpio@50008000 {
 				reg = <0x6000 0x400>;
 				clocks = <&rcc GPIOG>;
 				st,bank-name = "GPIOG";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1962,6 +1985,7 @@ gpioh: gpio@50009000 {
 				reg = <0x7000 0x400>;
 				clocks = <&rcc GPIOH>;
 				st,bank-name = "GPIOH";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1973,6 +1997,7 @@ gpioi: gpio@5000a000 {
 				reg = <0x8000 0x400>;
 				clocks = <&rcc GPIOI>;
 				st,bank-name = "GPIOI";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1984,6 +2009,7 @@ gpioj: gpio@5000b000 {
 				reg = <0x9000 0x400>;
 				clocks = <&rcc GPIOJ>;
 				st,bank-name = "GPIOJ";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1995,6 +2021,7 @@ gpiok: gpio@5000c000 {
 				reg = <0xa000 0x400>;
 				clocks = <&rcc GPIOK>;
 				st,bank-name = "GPIOK";
+				bootph-all;
 				status = "disabled";
 			};
 		};
@@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@54004000 {
 			ranges = <0 0x54004000 0x400>;
 			interrupt-parent = <&exti>;
 			st,syscfg = <&exti 0x60 0xff>;
+			bootph-all;
 
 			gpioz: gpio@54004000 {
 				gpio-controller;
@@ -2016,6 +2044,7 @@ gpioz: gpio@54004000 {
 				clocks = <&rcc GPIOZ>;
 				st,bank-name = "GPIOZ";
 				st,bank-ioport = <11>;
+				bootph-all;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
index 847b360f02fc..f721c398e576 100644
--- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
@@ -85,3 +85,17 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
+
+&uart4 {
+	bootph-all;
+};
+
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
index 0da3667ab1e0..c4581e28504a 100644
--- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
@@ -23,3 +23,46 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 };
+
+&i2c4 {
+	bootph-all;
+};
+
+&i2c4_pins_a {
+	bootph-all;
+	pins {
+		bootph-all;
+	};
+};
+
+&pmic {
+	bootph-all;
+};
+
+&sdmmc1 {
+	bootph-pre-ram;
+};
+
+&sdmmc1_b4_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
+&uart4 {
+	bootph-all;
+};
+
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
index 1ec3b8f2faa9..4fc670bb4cb0 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
@@ -79,6 +79,17 @@ touchscreen@38 {
 	};
 };
 
+&i2c4 {
+	bootph-all;
+};
+
+&i2c4_pins_a {
+	bootph-all;
+	pins {
+		bootph-all;
+	};
+};
+
 &ltdc {
 	status = "okay";
 
@@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 {
 	};
 };
 
+&pmic {
+	bootph-all;
+};
+
 &rtc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&rtc_rsvd_pins_a>;
@@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 {
 	};
 };
 
+&sdmmc1 {
+	bootph-pre-ram;
+};
+
+&sdmmc1_b4_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
 /* Wifi */
 &sdmmc2 {
 	pinctrl-names = "default", "opendrain", "sleep";
@@ -127,6 +156,20 @@ brcmf: wifi@1 {
 	};
 };
 
+&uart4 {
+	bootph-all;
+};
+
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 /* Bluetooth */
 &usart2 {
 	pinctrl-names = "default", "sleep", "idle";
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
index 6f27d794d270..00d4855f9a85 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
@@ -90,3 +90,17 @@ &rng1 {
 &rtc {
 	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
 };
+
+&uart4 {
+	bootph-all;
+};
+
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
index f6c478dbd041..f63a3d68d2b4 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
@@ -168,7 +168,9 @@ &i2c4 {
 	i2c-scl-rising-time-ns = <185>;
 	i2c-scl-falling-time-ns = <20>;
 	clock-frequency = <400000>;
+	bootph-all;
 	status = "okay";
+
 	/* spare dmas for other usage */
 	/delete-property/dmas;
 	/delete-property/dma-names;
@@ -179,6 +181,7 @@ pmic: stpmic@33 {
 		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
+		bootph-all;
 		status = "okay";
 
 		regulators {
@@ -314,6 +317,13 @@ watchdog {
 	};
 };
 
+&i2c4_pins_a {
+	bootph-all;
+	pins {
+		bootph-all;
+	};
+};
+
 &ipcc {
 	status = "okay";
 };
@@ -365,9 +375,30 @@ &sdmmc1 {
 	sd-uhs-sdr25;
 	sd-uhs-sdr50;
 	sd-uhs-ddr50;
+	bootph-pre-ram;
 	status = "okay";
 };
 
+&sdmmc1_b4_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
+&sdmmc1_dir_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
 &sdmmc2 {
 	pinctrl-names = "default", "opendrain", "sleep";
 	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
@@ -381,9 +412,27 @@ &sdmmc2 {
 	vmmc-supply = <&v3v3>;
 	vqmmc-supply = <&vdd>;
 	mmc-ddr-3_3v;
+	bootph-pre-ram;
 	status = "okay";
 };
 
+&sdmmc2_b4_pins_a {
+	bootph-pre-ram;
+	pins1 {
+		bootph-pre-ram;
+	};
+	pins2 {
+		bootph-pre-ram;
+	};
+};
+
+&sdmmc2_d47_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
 &timers6 {
 	status = "okay";
 	/* spare dmas for other usage */
@@ -399,11 +448,22 @@ &uart4 {
 	pinctrl-0 = <&uart4_pins_a>;
 	pinctrl-1 = <&uart4_sleep_pins_a>;
 	pinctrl-2 = <&uart4_idle_pins_a>;
+	bootph-all;
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "okay";
 };
 
+&uart4_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usbotg_hs {
 	vbus-supply = <&vbus_otg>;
 };
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
index 6ae391bffee5..bcf80f76d6bc 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
@@ -77,6 +77,31 @@ &optee {
 	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 };
 
+&qspi {
+	bootph-pre-ram;
+};
+
+&qspi_clk_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk1_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk2_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
 &rcc {
 	compatible = "st,stm32mp1-rcc-secure", "syscon";
 	clock-names = "hse", "hsi", "csi", "lse", "lsi";
diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
index 8f99c30f1af1..879436cbb72d 100644
--- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
@@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a
 	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	bootph-pre-ram;
 	status = "okay";
 
 	flash0: flash@0 {
@@ -283,6 +284,41 @@ flash1: flash@1 {
 	};
 };
 
+&qspi_clk_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk1_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_cs1_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_bk2_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
+&qspi_cs2_pins_a {
+	bootph-pre-ram;
+	pins {
+		bootph-pre-ram;
+	};
+};
+
 &sdmmc3 {
 	pinctrl-names = "default", "opendrain", "sleep";
 	pinctrl-0 = <&sdmmc3_b4_pins_a>;

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH v3 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards
  2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
                   ` (4 preceding siblings ...)
  2026-01-08 17:16 ` [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard
@ 2026-01-08 17:16 ` Patrice Chotard
  5 siblings, 0 replies; 9+ messages in thread
From: Patrice Chotard @ 2026-01-08 17:16 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
	Alexandre Torgue, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Patrice Chotard

The bootph-all flag was introduced in dt-schema
(dtschema/schemas/bootph.yaml) to define node usage across
different boot phases.

To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
present in all boot stages, so add missing bootph-all phase flag
to these nodes to support SD boot.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
---
 arch/arm64/boot/dts/st/stm32mp211.dtsi     |  7 +++++++
 arch/arm64/boot/dts/st/stm32mp215f-dk.dts  |  1 +
 arch/arm64/boot/dts/st/stm32mp231.dtsi     | 22 ++++++++++++++++++++++
 arch/arm64/boot/dts/st/stm32mp235f-dk.dts  | 11 +++++++++++
 arch/arm64/boot/dts/st/stm32mp251.dtsi     | 25 +++++++++++++++++++++++++
 arch/arm64/boot/dts/st/stm32mp255.dtsi     |  3 ++-
 arch/arm64/boot/dts/st/stm32mp257f-dk.dts  | 11 +++++++++++
 arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 11 +++++++++++
 8 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index bf888d60cd4f..81b6a71fc032 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -50,6 +50,7 @@ firmware {
 		optee {
 			compatible = "linaro,optee-tz";
 			method = "smc";
+			bootph-all;
 		};
 
 		scmi: scmi {
@@ -57,15 +58,18 @@ scmi: scmi {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
+			bootph-all;
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
+				bootph-all;
 			};
 		};
 	};
@@ -73,6 +77,7 @@ scmi_reset: protocol@16 {
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+		bootph-all;
 	};
 
 	timer {
@@ -92,6 +97,7 @@ soc@0 {
 		interrupt-parent = <&intc>;
 		#address-cells = <1>;
 		#size-cells = <2>;
+		bootph-all;
 
 		rifsc: bus@42080000 {
 			compatible = "simple-bus";
@@ -100,6 +106,7 @@ rifsc: bus@42080000 {
 			dma-ranges;
 			#address-cells = <1>;
 			#size-cells = <2>;
+			bootph-all;
 
 			usart2: serial@400e0000 {
 				compatible = "st,stm32h7-uart";
diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
index 7bdaeaa5ab0f..bc366639744a 100644
--- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
@@ -45,5 +45,6 @@ &arm_wdt {
 };
 
 &usart2 {
+	bootph-all;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 88e214d395ab..075b4419d3ae 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -57,6 +57,7 @@ optee: optee {
 			method = "smc";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+			bootph-all;
 		};
 
 		scmi {
@@ -64,15 +65,18 @@ scmi {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
+			bootph-all;
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_voltd: protocol@17 {
@@ -114,6 +118,7 @@ scmi_vdda18adc: regulator@7 {
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+		bootph-all;
 
 		cpu0_pd: power-domain-cpu0 {
 			#power-domain-cells = <0>;
@@ -146,6 +151,7 @@ soc@0 {
 		interrupt-parent = <&intc>;
 		#address-cells = <1>;
 		#size-cells = <1>;
+		bootph-all;
 
 		hpdma: dma-controller@40400000 {
 			compatible = "st,stm32mp25-dma3";
@@ -223,6 +229,7 @@ rifsc: bus@42080000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			#access-controller-cells = <1>;
+			bootph-all;
 
 			i2s2: audio-controller@400b0000 {
 				compatible = "st,stm32mp25-i2s";
@@ -760,6 +767,7 @@ bsec: efuse@44000000 {
 			reg = <0x44000000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			bootph-all;
 
 			part_number_otp@24 {
 				reg = <0x24 0x4>;
@@ -857,6 +865,7 @@ rcc: clock-controller@44200000 {
 				<&scmi_clk CK_SCMI_PLL3>,
 				<&clk_dsi_txbyte>;
 				access-controllers = <&rifsc 156>;
+			bootph-all;
 		};
 
 		exti1: interrupt-controller@44220000 {
@@ -955,6 +964,7 @@ exti1: interrupt-controller@44220000 {
 		syscfg: syscon@44230000 {
 			compatible = "st,stm32mp23-syscfg", "syscon";
 			reg = <0x44230000 0x10000>;
+			bootph-all;
 		};
 
 		pinctrl: pinctrl@44240000 {
@@ -965,6 +975,7 @@ pinctrl: pinctrl@44240000 {
 			interrupt-parent = <&exti1>;
 			st,syscfg = <&exti1 0x60 0xff>;
 			pins-are-numbered;
+			bootph-all;
 
 			gpioa: gpio@44240000 {
 				reg = <0x0 0x400>;
@@ -974,6 +985,7 @@ gpioa: gpio@44240000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOA>;
 				st,bank-name = "GPIOA";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -985,6 +997,7 @@ gpiob: gpio@44250000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOB>;
 				st,bank-name = "GPIOB";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -996,6 +1009,7 @@ gpioc: gpio@44260000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOC>;
 				st,bank-name = "GPIOC";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1007,6 +1021,7 @@ gpiod: gpio@44270000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOD>;
 				st,bank-name = "GPIOD";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1018,6 +1033,7 @@ gpioe: gpio@44280000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOE>;
 				st,bank-name = "GPIOE";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1029,6 +1045,7 @@ gpiof: gpio@44290000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOF>;
 				st,bank-name = "GPIOF";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1040,6 +1057,7 @@ gpiog: gpio@442a0000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOG>;
 				st,bank-name = "GPIOG";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1051,6 +1069,7 @@ gpioh: gpio@442b0000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOH>;
 				st,bank-name = "GPIOH";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1062,6 +1081,7 @@ gpioi: gpio@442c0000 {
 				#interrupt-cells = <2>;
 				clocks = <&scmi_clk CK_SCMI_GPIOI>;
 				st,bank-name = "GPIOI";
+				bootph-all;
 				status = "disabled";
 			};
 		};
@@ -1084,6 +1104,7 @@ pinctrl_z: pinctrl@46200000 {
 			interrupt-parent = <&exti1>;
 			st,syscfg = <&exti1 0x60 0xff>;
 			pins-are-numbered;
+			bootph-all;
 
 			gpioz: gpio@46200000 {
 				reg = <0 0x400>;
@@ -1094,6 +1115,7 @@ gpioz: gpio@46200000 {
 				clocks = <&scmi_clk CK_SCMI_GPIOZ>;
 				st,bank-name = "GPIOZ";
 				st,bank-ioport = <11>;
+				bootph-all;
 				status = "disabled";
 			};
 
diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
index c3e688068223..391494eda5e6 100644
--- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
@@ -130,7 +130,18 @@ &usart2 {
 	pinctrl-0 = <&usart2_pins_a>;
 	pinctrl-1 = <&usart2_idle_pins_a>;
 	pinctrl-2 = <&usart2_sleep_pins_a>;
+	bootph-all;
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "okay";
 };
+
+&usart2_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index a8e6e0f77b83..0cc3ac8bb584 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -66,6 +66,7 @@ optee: optee {
 			method = "smc";
 			interrupt-parent = <&intc>;
 			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+			bootph-all;
 		};
 
 		scmi {
@@ -73,15 +74,18 @@ scmi {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			linaro,optee-channel-id = <0>;
+			bootph-all;
 
 			scmi_clk: protocol@14 {
 				reg = <0x14>;
 				#clock-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_reset: protocol@16 {
 				reg = <0x16>;
 				#reset-cells = <1>;
+				bootph-all;
 			};
 
 			scmi_voltd: protocol@17 {
@@ -142,6 +146,7 @@ v2m0: v2m@48090000 {
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
+		bootph-all;
 
 		CPU_PD0: power-domain-cpu0 {
 			#power-domain-cells = <0>;
@@ -174,6 +179,7 @@ soc@0 {
 		#size-cells = <1>;
 		interrupt-parent = <&intc>;
 		ranges = <0x0 0x0 0x0 0x80000000>;
+		bootph-all;
 
 		hpdma: dma-controller@40400000 {
 			compatible = "st,stm32mp25-dma3";
@@ -305,6 +311,7 @@ rifsc: bus@42080000 {
 			#size-cells = <1>;
 			#access-controller-cells = <1>;
 			ranges;
+			bootph-all;
 
 			timers2: timer@40000000 {
 				compatible = "st,stm32mp25-timers";
@@ -1577,6 +1584,7 @@ ltdc: display-controller@48010000 {
 				clock-names = "lcd", "bus";
 				resets = <&rcc LTDC_R>;
 				access-controllers = <&rifsc 80>;
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1738,6 +1746,7 @@ bsec: efuse@44000000 {
 			reg = <0x44000000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			bootph-all;
 
 			part_number_otp@24 {
 				reg = <0x24 0x4>;
@@ -1842,6 +1851,7 @@ rcc: clock-controller@44200000 {
 				<&scmi_clk CK_SCMI_PLL3>,
 				<&clk_dsi_txbyte>;
 				access-controllers = <&rifsc 156>;
+			bootph-all;
 		};
 
 		exti1: interrupt-controller@44220000 {
@@ -1941,6 +1951,7 @@ syscfg: syscon@44230000 {
 			compatible = "st,stm32mp25-syscfg", "syscon";
 			reg = <0x44230000 0x10000>;
 			#clock-cells = <0>;
+			bootph-all;
 		};
 
 		pinctrl: pinctrl@44240000 {
@@ -1951,6 +1962,7 @@ pinctrl: pinctrl@44240000 {
 			interrupt-parent = <&exti1>;
 			st,syscfg = <&exti1 0x60 0xff>;
 			pins-are-numbered;
+			bootph-all;
 
 			gpioa: gpio@44240000 {
 				gpio-controller;
@@ -1960,6 +1972,7 @@ gpioa: gpio@44240000 {
 				reg = <0x0 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOA>;
 				st,bank-name = "GPIOA";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1971,6 +1984,7 @@ gpiob: gpio@44250000 {
 				reg = <0x10000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOB>;
 				st,bank-name = "GPIOB";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1982,6 +1996,7 @@ gpioc: gpio@44260000 {
 				reg = <0x20000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOC>;
 				st,bank-name = "GPIOC";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -1993,6 +2008,7 @@ gpiod: gpio@44270000 {
 				reg = <0x30000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOD>;
 				st,bank-name = "GPIOD";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2004,6 +2020,7 @@ gpioe: gpio@44280000 {
 				reg = <0x40000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOE>;
 				st,bank-name = "GPIOE";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2015,6 +2032,7 @@ gpiof: gpio@44290000 {
 				reg = <0x50000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOF>;
 				st,bank-name = "GPIOF";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2026,6 +2044,7 @@ gpiog: gpio@442a0000 {
 				reg = <0x60000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOG>;
 				st,bank-name = "GPIOG";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2037,6 +2056,7 @@ gpioh: gpio@442b0000 {
 				reg = <0x70000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOH>;
 				st,bank-name = "GPIOH";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2048,6 +2068,7 @@ gpioi: gpio@442c0000 {
 				reg = <0x80000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOI>;
 				st,bank-name = "GPIOI";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2059,6 +2080,7 @@ gpioj: gpio@442d0000 {
 				reg = <0x90000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOJ>;
 				st,bank-name = "GPIOJ";
+				bootph-all;
 				status = "disabled";
 			};
 
@@ -2070,6 +2092,7 @@ gpiok: gpio@442e0000 {
 				reg = <0xa0000 0x400>;
 				clocks = <&scmi_clk CK_SCMI_GPIOK>;
 				st,bank-name = "GPIOK";
+				bootph-all;
 				status = "disabled";
 			};
 		};
@@ -2092,6 +2115,7 @@ pinctrl_z: pinctrl@46200000 {
 			interrupt-parent = <&exti1>;
 			st,syscfg = <&exti1 0x60 0xff>;
 			pins-are-numbered;
+			bootph-all;
 
 			gpioz: gpio@46200000 {
 				gpio-controller;
@@ -2102,6 +2126,7 @@ gpioz: gpio@46200000 {
 				clocks = <&scmi_clk CK_SCMI_GPIOZ>;
 				st,bank-name = "GPIOZ";
 				st,bank-ioport = <11>;
+				bootph-all;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..7b2e07613030 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -21,6 +21,7 @@ lvds: lvds@48060000 {
 		resets = <&rcc LVDS_R>;
 		access-controllers = <&rifsc 84>;
 		power-domains = <&CLUSTER_PD>;
+		bootph-all;
 		status = "disabled";
 	};
 
@@ -40,4 +41,4 @@ venc: venc@480e0000 {
 		clocks = <&rcc CK_BUS_VENC>;
 		access-controllers = <&rifsc 90>;
 	};
-};
\ No newline at end of file
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
index e718d888ce21..69bac9e719d7 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
@@ -130,7 +130,18 @@ &usart2 {
 	pinctrl-0 = <&usart2_pins_a>;
 	pinctrl-1 = <&usart2_idle_pins_a>;
 	pinctrl-2 = <&usart2_sleep_pins_a>;
+	bootph-all;
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "okay";
 };
+
+&usart2_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 6e165073f732..307b9692b00a 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
@@ -477,11 +477,22 @@ &usart2 {
 	pinctrl-0 = <&usart2_pins_a>;
 	pinctrl-1 = <&usart2_idle_pins_a>;
 	pinctrl-2 = <&usart2_sleep_pins_a>;
+	bootph-all;
 	/delete-property/dmas;
 	/delete-property/dma-names;
 	status = "okay";
 };
 
+&usart2_pins_a {
+	bootph-all;
+	pins1 {
+		bootph-all;
+	};
+	pins2 {
+		bootph-all;
+	};
+};
+
 &usart6 {
 	pinctrl-names = "default", "idle", "sleep";
 	pinctrl-0 = <&usart6_pins_a>;

-- 
2.43.0


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
  2026-01-08 17:16 ` [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard
@ 2026-01-09  8:19   ` Alexandre TORGUE
  2026-01-09  9:09     ` Patrice CHOTARD
  0 siblings, 1 reply; 9+ messages in thread
From: Alexandre TORGUE @ 2026-01-09  8:19 UTC (permalink / raw)
  To: Patrice Chotard, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Maxime Coquelin, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel

Hi Patrice

On 1/8/26 18:16, Patrice Chotard wrote:
> The bootph-all flag was introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across
> different boot phases.
> 
> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
> present in all boot stages, so add missing bootph-all phase flag
> to these nodes to support SD boot.
> 
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
>   arch/arm/boot/dts/st/stm32mp15-scmi.dtsi      | 26 ++++++++++++
>   arch/arm/boot/dts/st/stm32mp151.dtsi          | 29 +++++++++++++
>   arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++
>   arch/arm/boot/dts/st/stm32mp157a-dk1.dts      | 43 +++++++++++++++++++
>   arch/arm/boot/dts/st/stm32mp157c-dk2.dts      | 43 +++++++++++++++++++
>   arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++
>   arch/arm/boot/dts/st/stm32mp157c-ed1.dts      | 60 +++++++++++++++++++++++++++
>   arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 25 +++++++++++
>   arch/arm/boot/dts/st/stm32mp157c-ev1.dts      | 36 ++++++++++++++++
>   9 files changed, 290 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
> index 98552fe45d4e..c58d81f505be 100644
> --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
> @@ -13,6 +13,7 @@ optee: optee {
>   			method = "smc";
>   			interrupt-parent = <&intc>;
>   			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
> +			bootph-some-ram;
>   		};
>   
>   		scmi: scmi {
> @@ -20,6 +21,7 @@ scmi: scmi {
>   			#address-cells = <1>;
>   			#size-cells = <0>;
>   			linaro,optee-channel-id = <0>;
> +			bootph-some-ram;
>   
>   			scmi_clk: protocol@14 {
>   				reg = <0x14>;
> @@ -64,6 +66,26 @@ scmi_usb33: regulator@2 {
>   	};
>   };
>   
> +&iwdg2 {
> +	bootph-all;
> +};
> 

node update useless as already done in stm32mp151.dtsi

> +&ltdc {
> +	bootph-some-ram;
> +};
> 

ditto

> +&pinctrl {
> +	bootph-all;
> +};
> +

ditto

> +&pinctrl_z {
> +	bootph-all;
> +};
> 
ditto

> +&rcc {
> +	bootph-all;
> +};
> 

ditto

>   &reg11 {
>   	status = "disabled";
>   };
> @@ -72,6 +94,10 @@ &reg18 {
>   	status = "disabled";
>   };
>   
> +&scmi {
> +	bootph-some-ram;
> +};

Already define at the top of this patch.



> +
>   &usb33 {
>   	status = "disabled";
>   };
> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
> index b1b568dfd126..7abee7ce0580 100644
> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
> @@ -33,6 +33,7 @@ arm-pmu {
>   	psci {
>   		compatible = "arm,psci-1.0";
>   		method = "smc";
> +		bootph-some-ram;
>   	};
>   
>   	intc: interrupt-controller@a0021000 {
> @@ -54,34 +55,41 @@ timer {
>   	};
>   
>   	clocks {
> +		bootph-all;
> +
>   		clk_hse: clk-hse {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <24000000>;
> +			bootph-all;
>   		};
>   
>   		clk_hsi: clk-hsi {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <64000000>;
> +			bootph-all;
>   		};
>   
>   		clk_lse: clk-lse {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <32768>;
> +			bootph-all;
>   		};
>   
>   		clk_lsi: clk-lsi {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <32000>;
> +			bootph-all;
>   		};
>   
>   		clk_csi: clk-csi {
>   			#clock-cells = <0>;
>   			compatible = "fixed-clock";
>   			clock-frequency = <4000000>;
> +			bootph-all;
>   		};
>   	};
>   
> @@ -122,6 +130,7 @@ soc {
>   		#size-cells = <1>;
>   		interrupt-parent = <&intc>;
>   		ranges;
> +		bootph-all;
>   
>   		ipcc: mailbox@4c001000 {
>   			compatible = "st,stm32mp1-ipcc";
> @@ -142,11 +151,13 @@ rcc: rcc@50000000 {
>   			reg = <0x50000000 0x1000>;
>   			#clock-cells = <1>;
>   			#reset-cells = <1>;
> +			bootph-all;
>   		};
>   
>   		pwr_regulators: pwr@50001000 {
>   			compatible = "st,stm32mp1,pwr-reg";
>   			reg = <0x50001000 0x10>;
> +			bootph-all;
>   
>   			reg11: reg11 {
>   				regulator-name = "reg11";
> @@ -354,6 +365,7 @@ ltdc: display-controller@5a001000 {
>   			clocks = <&rcc LTDC_PX>;
>   			clock-names = "lcd";
>   			resets = <&rcc LTDC_R>;
> +			bootph-some-ram;
>   			status = "disabled";
>   		};
>   
> @@ -364,6 +376,7 @@ iwdg2: watchdog@5a002000 {
>   			clock-names = "pclk", "lsi";
>   			interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>;
>   			wakeup-source;
> +			bootph-all;
>   			status = "disabled";
>   		};
>   
> @@ -404,6 +417,8 @@ bsec: efuse@5c005000 {
>   			reg = <0x5c005000 0x400>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
> +			bootph-all;
> +
>   			part_number_otp: part-number-otp@4 {
>   				reg = <0x4 0x1>;
>   			};
> @@ -1876,6 +1891,7 @@ pinctrl: pinctrl@50002000 {
>   			ranges = <0 0x50002000 0xa400>;
>   			interrupt-parent = <&exti>;
>   			st,syscfg = <&exti 0x60 0xff>;
> +			bootph-all;
>   
>   			gpioa: gpio@50002000 {
>   				gpio-controller;
> @@ -1885,6 +1901,7 @@ gpioa: gpio@50002000 {
>   				reg = <0x0 0x400>;
>   				clocks = <&rcc GPIOA>;
>   				st,bank-name = "GPIOA";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1896,6 +1913,7 @@ gpiob: gpio@50003000 {
>   				reg = <0x1000 0x400>;
>   				clocks = <&rcc GPIOB>;
>   				st,bank-name = "GPIOB";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1907,6 +1925,7 @@ gpioc: gpio@50004000 {
>   				reg = <0x2000 0x400>;
>   				clocks = <&rcc GPIOC>;
>   				st,bank-name = "GPIOC";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1918,6 +1937,7 @@ gpiod: gpio@50005000 {
>   				reg = <0x3000 0x400>;
>   				clocks = <&rcc GPIOD>;
>   				st,bank-name = "GPIOD";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1929,6 +1949,7 @@ gpioe: gpio@50006000 {
>   				reg = <0x4000 0x400>;
>   				clocks = <&rcc GPIOE>;
>   				st,bank-name = "GPIOE";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1940,6 +1961,7 @@ gpiof: gpio@50007000 {
>   				reg = <0x5000 0x400>;
>   				clocks = <&rcc GPIOF>;
>   				st,bank-name = "GPIOF";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1951,6 +1973,7 @@ gpiog: gpio@50008000 {
>   				reg = <0x6000 0x400>;
>   				clocks = <&rcc GPIOG>;
>   				st,bank-name = "GPIOG";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1962,6 +1985,7 @@ gpioh: gpio@50009000 {
>   				reg = <0x7000 0x400>;
>   				clocks = <&rcc GPIOH>;
>   				st,bank-name = "GPIOH";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1973,6 +1997,7 @@ gpioi: gpio@5000a000 {
>   				reg = <0x8000 0x400>;
>   				clocks = <&rcc GPIOI>;
>   				st,bank-name = "GPIOI";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1984,6 +2009,7 @@ gpioj: gpio@5000b000 {
>   				reg = <0x9000 0x400>;
>   				clocks = <&rcc GPIOJ>;
>   				st,bank-name = "GPIOJ";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   
> @@ -1995,6 +2021,7 @@ gpiok: gpio@5000c000 {
>   				reg = <0xa000 0x400>;
>   				clocks = <&rcc GPIOK>;
>   				st,bank-name = "GPIOK";
> +				bootph-all;
>   				status = "disabled";
>   			};
>   		};
> @@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@54004000 {
>   			ranges = <0 0x54004000 0x400>;
>   			interrupt-parent = <&exti>;
>   			st,syscfg = <&exti 0x60 0xff>;
> +			bootph-all;
>   
>   			gpioz: gpio@54004000 {
>   				gpio-controller;
> @@ -2016,6 +2044,7 @@ gpioz: gpio@54004000 {
>   				clocks = <&rcc GPIOZ>;
>   				st,bank-name = "GPIOZ";
>   				st,bank-ioport = <11>;
> +				bootph-all;
>   				status = "disabled";
>   			};
>   		};
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> index 847b360f02fc..f721c398e576 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> @@ -85,3 +85,17 @@ &rng1 {
>   &rtc {
>   	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>   };
> +
> +&uart4 {
> +	bootph-all;
> +};
> +
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
> index 0da3667ab1e0..c4581e28504a 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
> @@ -23,3 +23,46 @@ chosen {
>   		stdout-path = "serial0:115200n8";
>   	};
>   };
> +
> +&i2c4 {
> +	bootph-all;
> +};
> +
> +&i2c4_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
> +	};
> +};
> +
> +&pmic {
> +	bootph-all;
> +};
> +
> +&sdmmc1 {
> +	bootph-pre-ram;
> +};
> +
> +&sdmmc1_b4_pins_a {
> +	bootph-pre-ram;
> +	pins1 {
> +		bootph-pre-ram;
> +	};
> +	pins2 {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&uart4 {
> +	bootph-all;
> +};
> +
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> index 1ec3b8f2faa9..4fc670bb4cb0 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> @@ -79,6 +79,17 @@ touchscreen@38 {
>   	};
>   };
>   
> +&i2c4 {
> +	bootph-all;
> +};
> +
> +&i2c4_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
> +	};
> +};
> +
>   &ltdc {
>   	status = "okay";
>   
> @@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 {
>   	};
>   };
>   
> +&pmic {
> +	bootph-all;
> +};
> +
>   &rtc {
>   	pinctrl-names = "default";
>   	pinctrl-0 = <&rtc_rsvd_pins_a>;
> @@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 {
>   	};
>   };
>   
> +&sdmmc1 {
> +	bootph-pre-ram;
> +};
> +
> +&sdmmc1_b4_pins_a {
> +	bootph-pre-ram;
> +	pins1 {
> +		bootph-pre-ram;
> +	};
> +	pins2 {
> +		bootph-pre-ram;
> +	};
> +};
> +
>   /* Wifi */
>   &sdmmc2 {
>   	pinctrl-names = "default", "opendrain", "sleep";
> @@ -127,6 +156,20 @@ brcmf: wifi@1 {
>   	};
>   };
>   
> +&uart4 {
> +	bootph-all;
> +};
> +
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> +
>   /* Bluetooth */
>   &usart2 {
>   	pinctrl-names = "default", "sleep", "idle";
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> index 6f27d794d270..00d4855f9a85 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> @@ -90,3 +90,17 @@ &rng1 {
>   &rtc {
>   	clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>   };
> +
> +&uart4 {
> +	bootph-all;
> +};
> +
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> index f6c478dbd041..f63a3d68d2b4 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> @@ -168,7 +168,9 @@ &i2c4 {
>   	i2c-scl-rising-time-ns = <185>;
>   	i2c-scl-falling-time-ns = <20>;
>   	clock-frequency = <400000>;
> +	bootph-all;
>   	status = "okay";
> +
>   	/* spare dmas for other usage */
>   	/delete-property/dmas;
>   	/delete-property/dma-names;
> @@ -179,6 +181,7 @@ pmic: stpmic@33 {
>   		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
>   		interrupt-controller;
>   		#interrupt-cells = <2>;
> +		bootph-all;
>   		status = "okay";
>   
>   		regulators {
> @@ -314,6 +317,13 @@ watchdog {
>   	};
>   };
>   
> +&i2c4_pins_a {
> +	bootph-all;
> +	pins {
> +		bootph-all;
> +	};
> +};
> +
>   &ipcc {
>   	status = "okay";
>   };
> @@ -365,9 +375,30 @@ &sdmmc1 {
>   	sd-uhs-sdr25;
>   	sd-uhs-sdr50;
>   	sd-uhs-ddr50;
> +	bootph-pre-ram;
>   	status = "okay";
>   };
>   
> +&sdmmc1_b4_pins_a {
> +	bootph-pre-ram;
> +	pins1 {
> +		bootph-pre-ram;
> +	};
> +	pins2 {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&sdmmc1_dir_pins_a {
> +	bootph-pre-ram;
> +	pins1 {
> +		bootph-pre-ram;
> +	};
> +	pins2 {
> +		bootph-pre-ram;
> +	};
> +};
> +
>   &sdmmc2 {
>   	pinctrl-names = "default", "opendrain", "sleep";
>   	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> @@ -381,9 +412,27 @@ &sdmmc2 {
>   	vmmc-supply = <&v3v3>;
>   	vqmmc-supply = <&vdd>;
>   	mmc-ddr-3_3v;
> +	bootph-pre-ram;
>   	status = "okay";
>   };
>   
> +&sdmmc2_b4_pins_a {
> +	bootph-pre-ram;
> +	pins1 {
> +		bootph-pre-ram;
> +	};
> +	pins2 {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&sdmmc2_d47_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
>   &timers6 {
>   	status = "okay";
>   	/* spare dmas for other usage */
> @@ -399,11 +448,22 @@ &uart4 {
>   	pinctrl-0 = <&uart4_pins_a>;
>   	pinctrl-1 = <&uart4_sleep_pins_a>;
>   	pinctrl-2 = <&uart4_idle_pins_a>;
> +	bootph-all;
>   	/delete-property/dmas;
>   	/delete-property/dma-names;
>   	status = "okay";
>   };
>   
> +&uart4_pins_a {
> +	bootph-all;
> +	pins1 {
> +		bootph-all;
> +	};
> +	pins2 {
> +		bootph-all;
> +	};
> +};
> +
>   &usbotg_hs {
>   	vbus-supply = <&vbus_otg>;
>   };
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> index 6ae391bffee5..bcf80f76d6bc 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> @@ -77,6 +77,31 @@ &optee {
>   	interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>   };
>   
> +&qspi {
> +	bootph-pre-ram;
> +};
> +
> +&qspi_clk_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_bk1_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_bk2_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
>   &rcc {
>   	compatible = "st,stm32mp1-rcc-secure", "syscon";
>   	clock-names = "hse", "hsi", "csi", "lse", "lsi";
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> index 8f99c30f1af1..879436cbb72d 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> @@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a
>   	reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
>   	#address-cells = <1>;
>   	#size-cells = <0>;
> +	bootph-pre-ram;
>   	status = "okay";
>   
>   	flash0: flash@0 {
> @@ -283,6 +284,41 @@ flash1: flash@1 {
>   	};
>   };
>   
> +&qspi_clk_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_bk1_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_cs1_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_bk2_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
> +&qspi_cs2_pins_a {
> +	bootph-pre-ram;
> +	pins {
> +		bootph-pre-ram;
> +	};
> +};
> +
>   &sdmmc3 {
>   	pinctrl-names = "default", "opendrain", "sleep";
>   	pinctrl-0 = <&sdmmc3_b4_pins_a>;
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
  2026-01-09  8:19   ` Alexandre TORGUE
@ 2026-01-09  9:09     ` Patrice CHOTARD
  0 siblings, 0 replies; 9+ messages in thread
From: Patrice CHOTARD @ 2026-01-09  9:09 UTC (permalink / raw)
  To: Alexandre TORGUE, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Maxime Coquelin, Patrick Delaunay
  Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel



On 1/9/26 09:19, Alexandre TORGUE wrote:
> Hi Patrice
> 
> On 1/8/26 18:16, Patrice Chotard wrote:
>> The bootph-all flag was introduced in dt-schema
>> (dtschema/schemas/bootph.yaml) to define node usage across
>> different boot phases.
>>
>> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
>> present in all boot stages, so add missing bootph-all phase flag
>> to these nodes to support SD boot.
>>
>> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
>> ---
>>   arch/arm/boot/dts/st/stm32mp15-scmi.dtsi      | 26 ++++++++++++
>>   arch/arm/boot/dts/st/stm32mp151.dtsi          | 29 +++++++++++++
>>   arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 14 +++++++
>>   arch/arm/boot/dts/st/stm32mp157a-dk1.dts      | 43 +++++++++++++++++++
>>   arch/arm/boot/dts/st/stm32mp157c-dk2.dts      | 43 +++++++++++++++++++
>>   arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 14 +++++++
>>   arch/arm/boot/dts/st/stm32mp157c-ed1.dts      | 60 +++++++++++++++++++++++++++
>>   arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 25 +++++++++++
>>   arch/arm/boot/dts/st/stm32mp157c-ev1.dts      | 36 ++++++++++++++++
>>   9 files changed, 290 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> index 98552fe45d4e..c58d81f505be 100644
>> --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
>> @@ -13,6 +13,7 @@ optee: optee {
>>               method = "smc";
>>               interrupt-parent = <&intc>;
>>               interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
>> +            bootph-some-ram;
>>           };
>>             scmi: scmi {
>> @@ -20,6 +21,7 @@ scmi: scmi {
>>               #address-cells = <1>;
>>               #size-cells = <0>;
>>               linaro,optee-channel-id = <0>;
>> +            bootph-some-ram;
>>                 scmi_clk: protocol@14 {
>>                   reg = <0x14>;
>> @@ -64,6 +66,26 @@ scmi_usb33: regulator@2 {
>>       };
>>   };
>>   +&iwdg2 {
>> +    bootph-all;
>> +};
>>
> 
> node update useless as already done in stm32mp151.dtsi

you are right, i will remove this node.

> 
>> +&ltdc {
>> +    bootph-some-ram;
>> +};
>>
> 
> ditto


ok> 
>> +&pinctrl {
>> +    bootph-all;
>> +};
>> +
> 
> ditto

ok> 
>> +&pinctrl_z {
>> +    bootph-all;
>> +};
>>
> ditto
ok> 
>> +&rcc {
>> +    bootph-all;
>> +};
>>
> 
> ditto

ok> 
>>   &reg11 {
>>       status = "disabled";
>>   };
>> @@ -72,6 +94,10 @@ &reg18 {
>>       status = "disabled";
>>   };
>>   +&scmi {
>> +    bootph-some-ram;
>> +};
> 
> Already define at the top of this patch.

ok

Thanks
Patrice> 
> 
> 
>> +
>>   &usb33 {
>>       status = "disabled";
>>   };
>> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> index b1b568dfd126..7abee7ce0580 100644
>> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
>> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
>> @@ -33,6 +33,7 @@ arm-pmu {
>>       psci {
>>           compatible = "arm,psci-1.0";
>>           method = "smc";
>> +        bootph-some-ram;
>>       };
>>         intc: interrupt-controller@a0021000 {
>> @@ -54,34 +55,41 @@ timer {
>>       };
>>         clocks {
>> +        bootph-all;
>> +
>>           clk_hse: clk-hse {
>>               #clock-cells = <0>;
>>               compatible = "fixed-clock";
>>               clock-frequency = <24000000>;
>> +            bootph-all;
>>           };
>>             clk_hsi: clk-hsi {
>>               #clock-cells = <0>;
>>               compatible = "fixed-clock";
>>               clock-frequency = <64000000>;
>> +            bootph-all;
>>           };
>>             clk_lse: clk-lse {
>>               #clock-cells = <0>;
>>               compatible = "fixed-clock";
>>               clock-frequency = <32768>;
>> +            bootph-all;
>>           };
>>             clk_lsi: clk-lsi {
>>               #clock-cells = <0>;
>>               compatible = "fixed-clock";
>>               clock-frequency = <32000>;
>> +            bootph-all;
>>           };
>>             clk_csi: clk-csi {
>>               #clock-cells = <0>;
>>               compatible = "fixed-clock";
>>               clock-frequency = <4000000>;
>> +            bootph-all;
>>           };
>>       };
>>   @@ -122,6 +130,7 @@ soc {
>>           #size-cells = <1>;
>>           interrupt-parent = <&intc>;
>>           ranges;
>> +        bootph-all;
>>             ipcc: mailbox@4c001000 {
>>               compatible = "st,stm32mp1-ipcc";
>> @@ -142,11 +151,13 @@ rcc: rcc@50000000 {
>>               reg = <0x50000000 0x1000>;
>>               #clock-cells = <1>;
>>               #reset-cells = <1>;
>> +            bootph-all;
>>           };
>>             pwr_regulators: pwr@50001000 {
>>               compatible = "st,stm32mp1,pwr-reg";
>>               reg = <0x50001000 0x10>;
>> +            bootph-all;
>>                 reg11: reg11 {
>>                   regulator-name = "reg11";
>> @@ -354,6 +365,7 @@ ltdc: display-controller@5a001000 {
>>               clocks = <&rcc LTDC_PX>;
>>               clock-names = "lcd";
>>               resets = <&rcc LTDC_R>;
>> +            bootph-some-ram;
>>               status = "disabled";
>>           };
>>   @@ -364,6 +376,7 @@ iwdg2: watchdog@5a002000 {
>>               clock-names = "pclk", "lsi";
>>               interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>;
>>               wakeup-source;
>> +            bootph-all;
>>               status = "disabled";
>>           };
>>   @@ -404,6 +417,8 @@ bsec: efuse@5c005000 {
>>               reg = <0x5c005000 0x400>;
>>               #address-cells = <1>;
>>               #size-cells = <1>;
>> +            bootph-all;
>> +
>>               part_number_otp: part-number-otp@4 {
>>                   reg = <0x4 0x1>;
>>               };
>> @@ -1876,6 +1891,7 @@ pinctrl: pinctrl@50002000 {
>>               ranges = <0 0x50002000 0xa400>;
>>               interrupt-parent = <&exti>;
>>               st,syscfg = <&exti 0x60 0xff>;
>> +            bootph-all;
>>                 gpioa: gpio@50002000 {
>>                   gpio-controller;
>> @@ -1885,6 +1901,7 @@ gpioa: gpio@50002000 {
>>                   reg = <0x0 0x400>;
>>                   clocks = <&rcc GPIOA>;
>>                   st,bank-name = "GPIOA";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1896,6 +1913,7 @@ gpiob: gpio@50003000 {
>>                   reg = <0x1000 0x400>;
>>                   clocks = <&rcc GPIOB>;
>>                   st,bank-name = "GPIOB";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1907,6 +1925,7 @@ gpioc: gpio@50004000 {
>>                   reg = <0x2000 0x400>;
>>                   clocks = <&rcc GPIOC>;
>>                   st,bank-name = "GPIOC";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1918,6 +1937,7 @@ gpiod: gpio@50005000 {
>>                   reg = <0x3000 0x400>;
>>                   clocks = <&rcc GPIOD>;
>>                   st,bank-name = "GPIOD";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1929,6 +1949,7 @@ gpioe: gpio@50006000 {
>>                   reg = <0x4000 0x400>;
>>                   clocks = <&rcc GPIOE>;
>>                   st,bank-name = "GPIOE";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1940,6 +1961,7 @@ gpiof: gpio@50007000 {
>>                   reg = <0x5000 0x400>;
>>                   clocks = <&rcc GPIOF>;
>>                   st,bank-name = "GPIOF";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1951,6 +1973,7 @@ gpiog: gpio@50008000 {
>>                   reg = <0x6000 0x400>;
>>                   clocks = <&rcc GPIOG>;
>>                   st,bank-name = "GPIOG";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1962,6 +1985,7 @@ gpioh: gpio@50009000 {
>>                   reg = <0x7000 0x400>;
>>                   clocks = <&rcc GPIOH>;
>>                   st,bank-name = "GPIOH";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1973,6 +1997,7 @@ gpioi: gpio@5000a000 {
>>                   reg = <0x8000 0x400>;
>>                   clocks = <&rcc GPIOI>;
>>                   st,bank-name = "GPIOI";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1984,6 +2009,7 @@ gpioj: gpio@5000b000 {
>>                   reg = <0x9000 0x400>;
>>                   clocks = <&rcc GPIOJ>;
>>                   st,bank-name = "GPIOJ";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>   @@ -1995,6 +2021,7 @@ gpiok: gpio@5000c000 {
>>                   reg = <0xa000 0x400>;
>>                   clocks = <&rcc GPIOK>;
>>                   st,bank-name = "GPIOK";
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>           };
>> @@ -2006,6 +2033,7 @@ pinctrl_z: pinctrl@54004000 {
>>               ranges = <0 0x54004000 0x400>;
>>               interrupt-parent = <&exti>;
>>               st,syscfg = <&exti 0x60 0xff>;
>> +            bootph-all;
>>                 gpioz: gpio@54004000 {
>>                   gpio-controller;
>> @@ -2016,6 +2044,7 @@ gpioz: gpio@54004000 {
>>                   clocks = <&rcc GPIOZ>;
>>                   st,bank-name = "GPIOZ";
>>                   st,bank-ioport = <11>;
>> +                bootph-all;
>>                   status = "disabled";
>>               };
>>           };
>> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> index 847b360f02fc..f721c398e576 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
>> @@ -85,3 +85,17 @@ &rng1 {
>>   &rtc {
>>       clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>>   };
>> +
>> +&uart4 {
>> +    bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> +    bootph-all;
>> +    pins1 {
>> +        bootph-all;
>> +    };
>> +    pins2 {
>> +        bootph-all;
>> +    };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> index 0da3667ab1e0..c4581e28504a 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1.dts
>> @@ -23,3 +23,46 @@ chosen {
>>           stdout-path = "serial0:115200n8";
>>       };
>>   };
>> +
>> +&i2c4 {
>> +    bootph-all;
>> +};
>> +
>> +&i2c4_pins_a {
>> +    bootph-all;
>> +    pins {
>> +        bootph-all;
>> +    };
>> +};
>> +
>> +&pmic {
>> +    bootph-all;
>> +};
>> +
>> +&sdmmc1 {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&sdmmc1_b4_pins_a {
>> +    bootph-pre-ram;
>> +    pins1 {
>> +        bootph-pre-ram;
>> +    };
>> +    pins2 {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&uart4 {
>> +    bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> +    bootph-all;
>> +    pins1 {
>> +        bootph-all;
>> +    };
>> +    pins2 {
>> +        bootph-all;
>> +    };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> index 1ec3b8f2faa9..4fc670bb4cb0 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
>> @@ -79,6 +79,17 @@ touchscreen@38 {
>>       };
>>   };
>>   +&i2c4 {
>> +    bootph-all;
>> +};
>> +
>> +&i2c4_pins_a {
>> +    bootph-all;
>> +    pins {
>> +        bootph-all;
>> +    };
>> +};
>> +
>>   &ltdc {
>>       status = "okay";
>>   @@ -93,6 +104,10 @@ ltdc_ep1_out: endpoint@1 {
>>       };
>>   };
>>   +&pmic {
>> +    bootph-all;
>> +};
>> +
>>   &rtc {
>>       pinctrl-names = "default";
>>       pinctrl-0 = <&rtc_rsvd_pins_a>;
>> @@ -103,6 +118,20 @@ rtc_lsco_pins_a: rtc-lsco-0 {
>>       };
>>   };
>>   +&sdmmc1 {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&sdmmc1_b4_pins_a {
>> +    bootph-pre-ram;
>> +    pins1 {
>> +        bootph-pre-ram;
>> +    };
>> +    pins2 {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>>   /* Wifi */
>>   &sdmmc2 {
>>       pinctrl-names = "default", "opendrain", "sleep";
>> @@ -127,6 +156,20 @@ brcmf: wifi@1 {
>>       };
>>   };
>>   +&uart4 {
>> +    bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> +    bootph-all;
>> +    pins1 {
>> +        bootph-all;
>> +    };
>> +    pins2 {
>> +        bootph-all;
>> +    };
>> +};
>> +
>>   /* Bluetooth */
>>   &usart2 {
>>       pinctrl-names = "default", "sleep", "idle";
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> index 6f27d794d270..00d4855f9a85 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
>> @@ -90,3 +90,17 @@ &rng1 {
>>   &rtc {
>>       clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
>>   };
>> +
>> +&uart4 {
>> +    bootph-all;
>> +};
>> +
>> +&uart4_pins_a {
>> +    bootph-all;
>> +    pins1 {
>> +        bootph-all;
>> +    };
>> +    pins2 {
>> +        bootph-all;
>> +    };
>> +};
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> index f6c478dbd041..f63a3d68d2b4 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
>> @@ -168,7 +168,9 @@ &i2c4 {
>>       i2c-scl-rising-time-ns = <185>;
>>       i2c-scl-falling-time-ns = <20>;
>>       clock-frequency = <400000>;
>> +    bootph-all;
>>       status = "okay";
>> +
>>       /* spare dmas for other usage */
>>       /delete-property/dmas;
>>       /delete-property/dma-names;
>> @@ -179,6 +181,7 @@ pmic: stpmic@33 {
>>           interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
>>           interrupt-controller;
>>           #interrupt-cells = <2>;
>> +        bootph-all;
>>           status = "okay";
>>             regulators {
>> @@ -314,6 +317,13 @@ watchdog {
>>       };
>>   };
>>   +&i2c4_pins_a {
>> +    bootph-all;
>> +    pins {
>> +        bootph-all;
>> +    };
>> +};
>> +
>>   &ipcc {
>>       status = "okay";
>>   };
>> @@ -365,9 +375,30 @@ &sdmmc1 {
>>       sd-uhs-sdr25;
>>       sd-uhs-sdr50;
>>       sd-uhs-ddr50;
>> +    bootph-pre-ram;
>>       status = "okay";
>>   };
>>   +&sdmmc1_b4_pins_a {
>> +    bootph-pre-ram;
>> +    pins1 {
>> +        bootph-pre-ram;
>> +    };
>> +    pins2 {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&sdmmc1_dir_pins_a {
>> +    bootph-pre-ram;
>> +    pins1 {
>> +        bootph-pre-ram;
>> +    };
>> +    pins2 {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>>   &sdmmc2 {
>>       pinctrl-names = "default", "opendrain", "sleep";
>>       pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
>> @@ -381,9 +412,27 @@ &sdmmc2 {
>>       vmmc-supply = <&v3v3>;
>>       vqmmc-supply = <&vdd>;
>>       mmc-ddr-3_3v;
>> +    bootph-pre-ram;
>>       status = "okay";
>>   };
>>   +&sdmmc2_b4_pins_a {
>> +    bootph-pre-ram;
>> +    pins1 {
>> +        bootph-pre-ram;
>> +    };
>> +    pins2 {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&sdmmc2_d47_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>>   &timers6 {
>>       status = "okay";
>>       /* spare dmas for other usage */
>> @@ -399,11 +448,22 @@ &uart4 {
>>       pinctrl-0 = <&uart4_pins_a>;
>>       pinctrl-1 = <&uart4_sleep_pins_a>;
>>       pinctrl-2 = <&uart4_idle_pins_a>;
>> +    bootph-all;
>>       /delete-property/dmas;
>>       /delete-property/dma-names;
>>       status = "okay";
>>   };
>>   +&uart4_pins_a {
>> +    bootph-all;
>> +    pins1 {
>> +        bootph-all;
>> +    };
>> +    pins2 {
>> +        bootph-all;
>> +    };
>> +};
>> +
>>   &usbotg_hs {
>>       vbus-supply = <&vbus_otg>;
>>   };
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> index 6ae391bffee5..bcf80f76d6bc 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
>> @@ -77,6 +77,31 @@ &optee {
>>       interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
>>   };
>>   +&qspi {
>> +    bootph-pre-ram;
>> +};
>> +
>> +&qspi_clk_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_bk1_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_bk2_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>>   &rcc {
>>       compatible = "st,stm32mp1-rcc-secure", "syscon";
>>       clock-names = "hse", "hsi", "csi", "lse", "lsi";
>> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> index 8f99c30f1af1..879436cbb72d 100644
>> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
>> @@ -262,6 +262,7 @@ &qspi_bk2_sleep_pins_a
>>       reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
>>       #address-cells = <1>;
>>       #size-cells = <0>;
>> +    bootph-pre-ram;
>>       status = "okay";
>>         flash0: flash@0 {
>> @@ -283,6 +284,41 @@ flash1: flash@1 {
>>       };
>>   };
>>   +&qspi_clk_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_bk1_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_cs1_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_bk2_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>> +&qspi_cs2_pins_a {
>> +    bootph-pre-ram;
>> +    pins {
>> +        bootph-pre-ram;
>> +    };
>> +};
>> +
>>   &sdmmc3 {
>>       pinctrl-names = "default", "opendrain", "sleep";
>>       pinctrl-0 = <&sdmmc3_b4_pins_a>;
>>
> 


^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2026-01-09  9:09 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-01-08 17:15 [PATCH v3 0/6] Add boot phase tags for STMicroelectronics boards Patrice Chotard
2026-01-08 17:16 ` [PATCH v3 1/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f4 boards Patrice Chotard
2026-01-08 17:16 ` [PATCH v3 2/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics f7 boards Patrice Chotard
2026-01-08 17:16 ` [PATCH v3 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards Patrice Chotard
2026-01-08 17:16 ` [PATCH v3 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards Patrice Chotard
2026-01-08 17:16 ` [PATCH v3 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards Patrice Chotard
2026-01-09  8:19   ` Alexandre TORGUE
2026-01-09  9:09     ` Patrice CHOTARD
2026-01-08 17:16 ` [PATCH v3 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards Patrice Chotard

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