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From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Yaroslav Bolyukin" <iam@lach.pw>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
	"Leo Li" <sunpeng.li@amd.com>,
	"Rodrigo Siqueira" <siqueira@igalia.com>,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Christian König" <christian.koenig@amd.com>,
	"Wayne Lin" <Wayne.Lin@amd.com>,
	amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	"Yaroslav Bolyukin" <iam@lach.pw>
Subject: Re: [PATCH v7 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings
Date: Thu, 04 Dec 2025 14:11:02 +0200	[thread overview]
Message-ID: <b0b1567707c91806e3758bf0b678c2038dffb3c2@intel.com> (raw)
In-Reply-To: <20251202110218.9212-5-iam@lach.pw>

On Tue, 02 Dec 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> For timings v7 block revision >=1, revision field also contains a bit
> that indicates that the mode timings should only be used with fixed bits
> per pixel value specified in vesa vendor-specific block.
>
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>

On the EDID/DisplayID parts,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

but I'd like to get ack from e.g. Ville about the
dsc_passthrough_timings_support member in struct drm_display_mode.

> ---
>  drivers/gpu/drm/drm_displayid_internal.h |  2 ++
>  drivers/gpu/drm/drm_edid.c               | 12 ++++++++----
>  include/drm/drm_modes.h                  | 10 ++++++++++
>  3 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 72f107ae832f..724174b429f2 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -97,6 +97,7 @@ struct displayid_header {
>  	u8 ext_count;
>  } __packed;
>  
> +#define DISPLAYID_BLOCK_REV	GENMASK(2, 0)
>  struct displayid_block {
>  	u8 tag;
>  	u8 rev;
> @@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 {
>  	__le16 vsw;
>  } __packed;
>  
> +#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT	BIT(3)
>  struct displayid_detailed_timing_block {
>  	struct displayid_block base;
>  	struct displayid_detailed_timings_1 timings[];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index 380a9dda275f..b28ff4bafb1d 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6794,8 +6794,8 @@ static void update_display_info(struct drm_connector *connector,
>  }
>  
>  static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
> -							    const struct displayid_detailed_timings_1 *timings,
> -							    bool type_7)
> +							    const struct displayid_block *block,
> +							    const struct displayid_detailed_timings_1 *timings)
>  {
>  	struct drm_display_mode *mode;
>  	unsigned int pixel_clock = (timings->pixel_clock[0] |
> @@ -6811,11 +6811,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d
>  	unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1;
>  	bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15);
>  	bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15);
> +	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>  
>  	mode = drm_mode_create(dev);
>  	if (!mode)
>  		return NULL;
>  
> +	if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1)
> +		mode->dsc_passthrough_timings_support =
> +			block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT;
> +
>  	/* resolution is kHz for type VII, and 10 kHz for type I */
>  	mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
>  	mode->hdisplay = hactive;
> @@ -6848,7 +6853,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>  	int num_timings;
>  	struct drm_display_mode *newmode;
>  	int num_modes = 0;
> -	bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
>  	/* blocks must be multiple of 20 bytes length */
>  	if (block->num_bytes % 20)
>  		return 0;
> @@ -6857,7 +6861,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector,
>  	for (i = 0; i < num_timings; i++) {
>  		struct displayid_detailed_timings_1 *timings = &det->timings[i];
>  
> -		newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
> +		newmode = drm_mode_displayid_detailed(connector->dev, block, timings);
>  		if (!newmode)
>  			continue;
>  
> diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h
> index b9bb92e4b029..312e5c03af9a 100644
> --- a/include/drm/drm_modes.h
> +++ b/include/drm/drm_modes.h
> @@ -417,6 +417,16 @@ struct drm_display_mode {
>  	 */
>  	enum hdmi_picture_aspect picture_aspect_ratio;
>  
> +	/**
> +	 * @dsc_passthrough_timing_support:
> +	 *
> +	 * Indicates whether this mode timing descriptor is supported
> +	 * with specific target DSC bits per pixel only.
> +	 *
> +	 * VESA vendor-specific data block shall exist with the relevant
> +	 * DSC bits per pixel declaration when this flag is set to true.
> +	 */
> +	bool dsc_passthrough_timings_support;
>  };
>  
>  /**

-- 
Jani Nikula, Intel

  reply	other threads:[~2025-12-04 12:11 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-02 11:02 [PATCH v7 0/7] VESA DisplayID fixed DSC BPP value support Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-12-02 11:02 ` [PATCH v7 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-12-04 12:08   ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-12-04 12:11   ` Jani Nikula [this message]
2025-12-02 11:02 ` [PATCH v7 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-12-04 12:11   ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-12-04 12:12   ` Jani Nikula
2025-12-02 11:02 ` [PATCH v7 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
2025-12-29  2:25   ` Lin, Wayne
2026-01-08 20:45 ` [PATCH v7 0/7] VESA DisplayID fixed DSC BPP value support Yaroslav Bolyukin
2026-01-09  8:15   ` Jani Nikula

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